Table 8-13: Ras#-To-Cas# Delay Timing Select; Vancouver Design Center - Epson S1D13505 Technical Manual

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Vancouver Design Center

bit 4
REG[22h] bit 4
bits 3-2
Hardware Functional Specification
Issue Date: 01/02/02
RAS#-to-CAS# Delay Value (N
This bit selects the DRAM RAS#-to-CAS# delay parameter, t
(N ) of MCLK periods (T
RCD
access time, t . Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.
RAC
N = Round-Up((t
RCD RAC
= 2
= Round-Up(t
RAC
= Round-Up(t
RAC
Note that for EDO-DRAM and N
N . This is done to satisfy the CAS# address setup time, t
RCD
The resulting t is related to N
RC
t = (N ) T
RCD RCD
t = (1.5) T
RCD M
t = (N + 0.5) T
RCD RCD
t = (N ) T
RCD RCD

Table 8-13: RAS#-to-CAS# Delay Timing Select

0
1
RAS# Precharge Timing Value (N
Minimum Memory Timing for RAS# precharge
These bits select the DRAM RAS# Precharge timing parameter, t
(N ) of MCLK periods (T
RP
assume an MCLK duty cycle of 50 +/- 5%.
N = 1
RP
= 1.5
= 2
The resulting t is related to N
RC
t = (N + 0.5) T
RP RP
t = (N ) T
RP RP M
)
RCD
) used to create t . N
M RCD
+ 5)/T - 1) if EDO and N
M
if EDO and N
/T - 1) if FPM and N
M
/T - 0.45) if FPM and N
M
= 1.5, this bit is automatically forced to 0 to select 2 MCLK for
RP
as follows:
RCD
if EDO and N
M RP
if EDO and N
RP
if FPM and N
M RP
if FPM and N
M RP
N
RCD
2
1
) Bits [1:0]
RP
) used to create t – see the following formulae. Note, these formulae
M RP
if (t /T ) < 1
RP M
if 1 (t /T ) < 1.45
RP M
if (t /T ) 1.45
RP M
as follows:
RP
if FPM refresh cycle and N
M
for all other
. This bit specifies the number
RCD
must be chosen to satisfy the RAS#
RCD
= 1 or 2
RP
= 1.5
RP
= 1 or 2
RP
= 1.5
RP
.
ASC
= 1 or 2
= 1.5
= 1 or 2
= 1.5
RAS#-to-CAS# Delay (t
RCD
2
1
. These bits specify the number
RP
= 1 or 2
RP
Page 115
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S1D13505
X23A-A-001-14