Fpm-Dram Cas Before Ras Refresh Timing; Table 7-19: Fpm-Dram Cas Before Ras Refresh Timing; Figure 7-20: Fpm-Dram Cas Before Ras Refresh Timing; Vancouver Design Center - Epson S1D13505 Technical Manual

Page 72

7.3.5 FPM-DRAM CAS Before RAS Refresh Timing

Symbol
t1 Internal memory clock period
RAS# precharge time (REG[22h] bits 3-2 = 00)
t2
RAS# precharge time (REG[22h] bits 3-2 = 01 or 10)
RAS# pulse width (REG[22h] bits 6-5 = 00 and bits 3-
2 = 00)
RAS# pulse width (REG[22h] bits 6-5 = 00 and bits 3-
2 = 01 or 10)
RAS# pulse width (REG[22h] bits 6-5 = 01 and bits 3-
2 = 00)
t3
RAS# pulse width (REG[22h] bits 6-5 = 01 and bits 3-
2 = 01 or 10)
RAS# pulse width (REG[22h] bits 6-5 = 10 and bits 3-
2 = 00)
RAS# pulse width (REG[22h] bits 6-5 = 10 and bits 3-
2 = 01 or 10)
CAS# pulse width (REG[22h] bits 3-2 = 00)
t4
CAS# pulse width (REG[22h] bits 3-2 = 01 or 10)
t5 CAS# Setup to RAS#
CAS# Hold to RAS# (REG[22h] bits 6-5 = 00 and bits
3-2 = 00)
CAS# Hold to RAS# (REG[22h] bits 6-5 = 00 and bits
3-2 = 01 or 10)
CAS# Hold to RAS# (REG[22h] bits 6-5 = 01 and bits
3-2 = 00)
t6
CAS# Hold to RAS# (REG[22h] bits 6-5 = 01 and bits
3-2 = 01 or 10)
CAS# Hold to RAS# (REG[22h] bits 6-5 = 10 and bits
3-2 = 00)
CAS# Hold to RAS# (REG[22h] bits 6-5 = 10 and bits
3-2 = 01 or 10)
S1D13505
X23A-A-001-14
t1
Memory
Clock
t2
RAS#
t4
CAS#

Figure 7-20: FPM-DRAM CAS Before RAS Refresh Timing

Table 7-19: FPM-DRAM CAS Before RAS Refresh Timing

Parameter
t3
t5
t6
Min
40
2.45 t1 - 3
1.45 t1 - 3
2.45 t1 - 3
3.45 t1 - 3
1.45 t1 - 3
2.45 t1 - 3
0.45 t1 - 3
1.45 t1 - 3
2 t1 - 3
1 t1 - 3
0.45 t1 - 3
2.45 t1 - 3
3.45 t1 - 3
1.45 t1 - 3
2.45 t1 - 3
0.45 t1 - 3
1.45 t1 - 3
Epson Research and Development

Vancouver Design Center

Max Units
Hardware Functional Specification
Issue Date: 01/02/02
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns