Figure 3-5: Typical System Diagram (Generic Bus); Figure 3-6: Typical System Diagram (Nec Vr41Xx (Mips) Bus) - Epson S1D13505 Technical Manual

Epson Research and Development
Vancouver Design Center
Generic
BUS
A[27:21]
CSn#
A[20:0]
D[15:0]
WE0#
WE1#
RD#
WAIT#
BCLK
RESET#
MIPS
BUS
A[25:21]
CSn#
A[20:0]
D[15:0]
MEMW#
SBHE#
MEMR#
RDY
BCLK
RESET
Hardware Functional Specification
Issue Date: 01/02/02
Power
Management
M/R#
Decoder
CS#
AB[20:0]
DB[15:0]
WE0#
WE1#
RD#
RD/WR#
WAIT#
BUSCLK
RESET#

Figure 3-5: Typical System Diagram (Generic Bus)

Power
Management
M/R#
Decoder
CS#
AB[20:0]
DB[15:0]
WE0#
WE1#
RD#
VDD
RD/WR#
WAIT#
BUSCLK
RESET#

Figure 3-6: Typical System Diagram (NEC VR41xx (MIPS) Bus)

.
Oscillator
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
FPFRAME
FPLINE
S1D13505F00A
LCDPWR
RED,GREEN,BLUE
1Mx16
FPM/EDO-DRAM
.
Oscillator
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
FPFRAME
FPLINE
S1D13505F00A
LCDPWR
RED,GREEN,BLUE
1Mx16
FPM/EDO-DRAM
UD[7:0]
LD[7:0]
4/8/16-bit
FPSHIFT
LCD
Display
FPFRAME
FPLINE
DRDY
MOD
CRT
HRTC
Display
VRTC
IREF
IREF
UD[7:0]
LD[7:0]
4/8/16-bit
FPSHIFT
LCD
FPFRAME Display
FPLINE
DRDY
MOD
CRT
HRTC
Display
VRTC
IREF
IREF
X23A-A-001-14
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S1D13505