Examples - Epson S1D13505 Technical Manual

Epson Research and Development
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REG[18h] Pixel Panning Register
Screen 2 Screen 2
Pixel Pan Bit Pixel Pan Bit
3 2

5.2.2 Examples

Note
Programming Notes and Examples
Issue Date: 01/02/05
Table 5-1: Number of Pixels Panned Using Start Address
Color Depth (bpp) Pixels per Word
1
2
4
8
15
16
Screen 2 Screen 2
Pixel Pan Bit Pixel Pan Bit
1 0
Figure 5-4: Pixel Panning Register
The pixel panning register offers finer control over pixel pans than is available with the
Start Address Registers. Using this register it is possible to pan the displayed image one
pixel at a time. Depending on the current color depth certain bits of the pixel pan register
are not used. The following table shows this.
Table 5-2: Active Pixel Pan Bits
Color Depth (bpp)
1
2
4
8
15/16
For the examples in this section assume that the display system has been set up to view a
640x480 pixel image in a 320x240 viewport. Refer to Section 2, "Initialization" on page 12
and Section 5.1, "Virtual Display" on page 29 for assistance with these settings.
Example 3: Panning - Right and Left
To pan to the right, increment the pixel pan value. If the pixel pan value is equal to the
current color depth then set the pixel pan value to zero and increment the start address
value. To pan to the left decrement the pixel pan value. If the pixel pan value is less than
zero set it to the color depth (bpp) less one and decrement the start address.
Scrolling operations are easier to follow if a value, call it pan_value, is used to track
both the pixel pan and start address. The least significant bits of pan_value will repre-
sent the pixel pan value and the more significant bits are the start address value.
Number of Pixels Panned
16
8
4
2
1
1
Screen 1 Screen 1
Pixel Pan Bit Pixel Pan Bit
3 2
Pixel Pan bits used
bits [3:0]
bits [2:0]
bits [1:0]
bit 0
---
16
8
4
2
1
1
Screen 1 Screen 1
Pixel Pan Bit Pixel Pan Bit
1 0
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S1D13505
X23A-G-003-07