Epson S1D13505 Technical Manual page 413

Epson Research and Development
Vancouver Design Center
Pin # FPGA Signal
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Evaluation Board User Manual
Issue Date: 01/02/05
Table 3-2: Connectors Pinout for Channel A6
S1D13505 Signal
chA6p1 CS#
chA6p2 BS#
chA6p3 WE0#
chA6p4 RD/WR#
chA6p5 WAIT#
chA6p6 N/C
chA6p7 N/C
chA6p8 N/C
chA6p9 N/C
chA6p10 N/C
ib1 XL
ib2 XR
ib3 YU
ib4 YL
ib5 N/C
ib6 N/C
ib7 N/C
ib8 XY
GND GND
GND GND
Channel A6
Pin #
SmXY
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
FPGA Signal S1D13505 Signal
dc5v DC5V
GND GND
dc3v DC3V
GND GND
dc3v DC3V
GND GND
dc3vs N/C
GND GND
dc12v DC12V
GND GND
battery N/C
GND GND
dcXA N/C
base5vDc N/C
dcXB N/C
GND GND
dcXC N/C
GND GND
senseH N/C
senseL N/C
S5U13505-D9000
X23A-G-002-04
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