8-Bit Single Color Passive Lcd Panel Timing (Format 2); Figure 7-32: 8-Bit Single Color Passive Lcd Panel Timing (Format 2); Vancouver Design Center - Epson S1D13505 Technical Manual

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7.5.5 8-Bit Single Color Passive LCD Panel Timing (Format 2)

FPFRAME
FPLINE
MOD
UD[3:0], LD[3:0]
FPLINE
MOD
FPSHIFT
UD3
UD2
UD1
UD0
LD3
LD2
LD1
LD0
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
VDP = Vertical Display Period
VNDP = Vertical Non-Display Period
HDP = Horizontal Display Period
HNDP = Horizontal Non-Display Period
S1D13505
X23A-A-001-14
LINE1 LINE2 LINE3
1-R1 1-B3 1-G6
1-G1 1-R4 1-B6
1-B1 1-G 4 1-R7
1-R2 1-B4 1-G7
1-G2 1-R5 1-B7
1-B2 1-G5 1-R8
1-R3 1-B5 1-G8
1-G3 1-R6 1-B8

Figure 7-32: 8-Bit Single Color Passive LCD Panel Timing (Format 2)

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
= ((REG[05h] bits [4:0]) + 1)*8Ts
VDP
LINE4 LINE479 LINE480
HDP
Epson Research and Development

Vancouver Design Center

VNDP
LINE1 LINE2
HNDP
1-G638
1-B638
1-R639
1-G639
1-B639
1-R640
1-G640
1-B640
Hardware Functional Specification
Issue Date: 01/02/02