Memory Mapping And Aliasing - Epson S1D13505 Technical Manual

Page 14

4.4 Memory Mapping and Aliasing

S1D13505
X23A-G-011-04
The NEC V 4121 provides the internal address decoding required by an external LCD
R
controller. The physical address range from 0A00 0000h to 0AFF FFFFh (16M bytes) is
reserved for use by an external LCD controller (e.g. S1D13505).
The S1D13505 supports up to 2M bytes of display buffer. The NEC V
ADD21 (connected to M/R#) is used to select between the S1D13505 display buffer
(ADD21=1) and the S1D13505 internal registers (ADD21=0). NEC V
ADD[23:22] are ignored, thus the S1D13505 is aliased four times at 4M byte intervals over
the LCD controller address range. Address lines ADD[25:24] are set at 10b and never
change while the LCD controller is being addressed.
Epson Research and Development
Vancouver Design Center
4121 address line
R
4121 address lines
R
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/05