Figure 7-45: Crt A.c. Timing; Vancouver Design Center - Epson S1D13505 Technical Manual

Page 98
VRTC
HRTC
Symbol
t1
VRTC cycle time
t2
VRTC pulse width low
VRTC falling edge to FPLINE falling edge
t3
phase difference
1. t8 = [((REG[09h] bits 1:0, REG[08h] bits 7:0)+1) + ((REG[0Ah] bits 6:0)+1)] lines
min
2. t9 = [((REG[0Ch] bits 2:0)+1)] lines
min
3. t12 = [((REG[06h] bits 4:0)+1)*8] Ts
min
S1D13505
X23A-A-001-14
t2
t3

Figure 7-45: CRT A.C. Timing

Parameter
Epson Research and Development
t1
Min Typ Max
note 1
note 2
note 3
Hardware Functional Specification

Vancouver Design Center

Units
Issue Date: 01/02/02