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11 SERIAL INTERFACE
11.1 Configuration of Serial Interface
The S1C88655 incorporates a full duplex serial
interface (when asynchronous system is selected)
that allows the user to select either clock synchro-
nous system or asynchronous system.
The data transfer method can be selected in
software. When the clock synchronous system is
selected, 8-bit data transfer is possible. When the
asynchronous system is selected, either 7-bit or 8-
bit data transfer is possible, and a parity check of
received data and the addition of a parity bit for
transmitting data can automatically be done by
selecting in software. Figure 11.1.1 shows the
configuration of the serial interface.
Note: Ch. 0 and Ch. 1 have the same circuit
configuration and functions. The signal and
control bit names are suffixed by a 0 or 1 to
indicate the channel number, enabling
discrimination between channels 0 and 1. In
this manual, however, channel numbers 0
and 1 are replaced with "x" unless
discrimination is necessary, because
explanations are common to both channels.
11.2 Switching Terminal Functions
The serial interface Ch. 0 input/output terminals,
___________
SIN0, SOUT0, SCLK0, and SRDY0 are shared with
the I/O ports P10–P13. Also Ch. 1 input/output
terminals, SIN1, SOUT1, SCLK1, and SRDY1 are
shared with the I/O ports P14–P17. In order to
utilize these terminals for the serial interface input/
output terminals, "1" must be written to the ESIFx
register. At initial reset, these terminals are set as I/
O port terminals.
Serial I/O control
& status register
Serial input
SIN0(P10)
control circuit
or SIN1(P14)
Start bit
detection circuit
SCLK0(P12)
or SCLK1(P16)
S1C88655 TECHNICAL MANUAL
___________
___________
___________
Data bus
Receive
Error detection
data buffer
circuit
Receive data
shift register
Clock
control circuit
Fig. 11.1.1 Configuration of serial interface
The direction of I/O port terminals set for serial
interface input/output terminals are determined by
the signal and transfer mode for each terminal.
Furthermore, the settings for the corresponding I/
O control registers for the I/O ports become
invalid.
Table 11.2.1 Configuration of input/output terminals
Terminal
When serial interface is selected
P10
P11
P12
P13
P14
P15
P16
P17
* The terminals used may vary depending on the transfer mode.
The serial interface terminals are configured
according to the transfer mode set using the
registers SMDx0 and SMDx1. SINx and SOUTx are
serial data input and output terminals which
function identically in clock synchronous system
and asynchronous system. SCLKx is exclusively for
use with clock synchronous system and functions
as a synchronous clock input/output terminal.
___________
SRDYx is exclusively for use in clock synchronous
slave mode and functions as a send-receive ready
signal output terminal. When asynchronous system
___________
is selected, since SCLKx and SRDYx are
superfluous, the I/O port terminals P12 (P16) and
P13 (P17) can be used as I/O ports. In the same
way, when clock synchronous master mode is
___________
selected, since SRDYx is superfluous, the I/O port
terminal P13 (P17) can be used as an I/O port.
Transmit
data buffer
Transmit data
shift register
Programmable timer 1 underflow signal (Ch. 0)
Programmable timer 7 underflow signal (Ch. 1)
EPSON
11 SERIAL INTERFACE
SIN0
SOUT0
SCLK0
SRDY0
SIN1
SOUT1
SCLK1
SRDY1
___________
___________
Interrupt
Interrupt
control circuit
request
Serial output
SOUT0(P11)
control circuit
or SOUT1(P15)
READY output
SRDY0(P13)
control circuit
or SRDY1(P17)
73
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