Epson S1D13505 Technical Manual page 278

Page 14
S1D13505
X23A-B-001-04
CRT PCLK
Source
Divide
Timing
MCLK
Source
Divide
Timing
These settings select the signal source and input clock
divisor for the CRT pixel clock (CRT PCLK).
The CRT PCLK source is CLKI.
Specifies the divide ratio of CLKI to derive the CRT
PCLK.
Selecting "Auto" for the divisor allows the configu-
ration program to calculate the best clock divisor.
Unless a very specific clocking is required, it is best to
leave this setting on "Auto".
This field shows the actual CRT PCLK frequency used
by the configuration process calculations.
These settings select the signal source and input clock
divisor for the memory clock (MCLK).
The MCLK source is CLKI.
Specifies the divide ratio of CLKI to derive MCLK.
Leave this setting at 1:1 ratio unless MCLK is greater
than 40MHz.
This field shows the actual MCLK frequency used by
the configuration process calculations.
Epson Research and Development
Vancouver Design Center
13505CFG Configuration Program
Issue Date: 01/03/29