Edo-Dram Self-Refresh Timing; Table 7-17: Edo-Dram Self-Refresh Timing; Figure 7-17: Edo-Dram Self-Refresh Timing; Vancouver Design Center - Epson S1D13505 Technical Manual

Page 68

7.3.3 EDO-DRAM Self-Refresh Timing

Memory
Clock
RAS#
CAS#
Symbol
t1
Internal memory clock period
RAS# precharge time (REG[22h] bits 3-2 = 00)
t2 RAS# precharge time (REG[22h] bits 3-2 = 01)
RAS# precharge time (REG[22h] bits 3-2 = 10)
RAS# to CAS# precharge time (REG[22h] bits 3-2 = 00)
t3
RAS# to CAS# precharge time (REG[22h] bits 3-2 = 01 or 10)
CAS# setup time (REG[22h] bits 3-2 = 00 or 10)
t4
CAS# setup time (REG[22h] bits 3-2 = 01)
CAS# precharge time (REG[22h] bits 3-2 = 00)
t5
CAS# precharge time (REG[22h] bits 3-2 = 01 or 10)
S1D13505
X23A-A-001-14
Stopped for
suspend mode
t1
t2
t3 t4
t5

Figure 7-17: EDO-DRAM Self-Refresh Timing

Table 7-17: EDO-DRAM Self-Refresh Timing

Parameter
Epson Research and Development
Restarted for
active mode
Min
25
2 t1 - 3
1.45t1 - 3
1 t1 - 3
1.45t1 - 3
0.45t1 - 3
0.45t1 - 3
1 t1 - 3
2 t1 - 3
1 t1 - 3
Hardware Functional Specification

Vancouver Design Center

Max Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Issue Date: 01/02/02