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Epson Research and Development
Vancouver Design Center
Symbol
t1
Clock period
t2
Clock pulse width low
t3
Clock pulse width high
t4
AB[11:31], RD/WR#, TSIZ[0:1], M/R# setup
t5
AB[11:31], RD/WR#, TSIZ[0:1], M/R# hold
t6
CS# setup
t7
CS# hold
t8
TS# setup
t9
TS# hold
t10
CLKOUT to TA# driven
t11
CLKOUT to TA# low
t12
CLKOUT to TA# high
t13
negative edge CLKOUT to TA# tri-state
t14
CLKOUT to BI# driven
t15
CLKOUT to BI# high
t16
negative edge CLKOUT to BI# tri-state
t17
D[0:15] setup to 2nd CLKOUT after TS# = 0 (write cycle)
t18
D[0:15] hold (write cycle)
t19
CLKOUT to D[0:15] driven (read cycle)
t20
D[0:15] valid to TA# falling edge (read cycle)
t21
CLKOUT to D[0:15] tri-state (read cycle)
Hardware Functional Specification
Issue Date: 01/02/02
Table 7-12: Power PC Timing
Parameter
3.0V
5.0V
Min
Max
Min
25
20
6
6
6
6
10
10
0
0
10
10
0
0
7
10
5
0
0
0
3
19
3
3
19.7
3
5
25
2.5
0
18
0
3
16
3
5
25
2.5
10
10
0
0
0
0
0
0
5
25
2.5
Page 61
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
ns
13
ns
10
ns
11
ns
10
ns
10
ns
ns
ns
ns
ns
10
ns
S1D13505
X23A-A-001-14
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