Table 7-4: Mc68030 Timing; Vancouver Design Center - Epson S1D13505 Technical Manual

Epson Research and Development

Vancouver Design Center

Symbol
t1
Clock period
t2
Clock pulse width high
t3
Clock pulse width low
A[20:0], SIZ[1:0], M/R# setup to first CLK where CS# = 0 AS# =
t4
0, and either UDS#=0 or LDS# = 0
t5
A[20:0], SIZ[1:0], M/R# hold from AS#
t6
CS# hold from AS#
t7
R/W# setup to DS#
t8
R/W# hold from AS#
1
t9
AS# = 0 and CS# = 0 to DSACK1# driven high
t10
AS# high to DSACK1# high
t11
First BCLK where AS# = 1 to DSACK1# high impedance
D[31:16] valid to third CLK where CS# = 0 AS# = 0, and either
t12
UDS#=0 or LDS# = 0 (write cycle)
t13
D[31:16] hold from falling edge of DSACK1# (write cycle)
Falling edge of UDS#=0 or LDS# = 0 to D[31:16] driven (read
2
t14
cycle)
t15
D[31:16] valid to DSACK1# falling edge (read cycle)
UDS# and LDS# high to D[31:16] invalid/high impedance (read
t16
cycle)
t17
AS# high setup to CLK
Hardware Functional Specification
Issue Date: 01/02/02

Table 7-4: MC68030 Timing

Parameter
1. If the S1D13505 host interface is disabled, the timing for DSACK1# driven high is relative to
the falling edge of CS#, AS# or the first positive edge of CLK after A[20:0], M/R# becomes
valid, whichever one is later.
2. If the S1D13505 host interface is disabled, the timing for D[31:16] driven is relative to the
falling edge of UDS#, LDS# or the first positive edge of CLK after A[20:0], M/R# becomes
valid, whichever one is later.
3.0V 5.0V
Min Max Min
20 20
6 6
6 6
10 10
0 0
0 0
10 10
0 0
0 0
3 18 3
5 25 2.5
10 10
0 0
0 0
0 0
5 25 2.5
2 2
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Max Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
12 ns
10 ns
ns
ns
ns
ns
10 ns
ns
S1D13505
X23A-A-001-14