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Page 48
REG[0Dh] Display Mode Register
Simultaneous
SwivelView
Display
Enable
Option Select
Bit 1
REG[10h] Screen 1 Display Start Address Register 0
Bit 7
Bit 6
REG[11h] Screen 1 Display Start Address Register 1
Bit 15
Bit 14
REG[12h] Screen 1 Display Start Address Register 2
n/a
n/a
REG[16h] Memory Address Offset Register 0
Bit 7
Bit 6
REG[17h] Memory Address Offset Register 1
n/a
n/a
8.4 Limitations
S1D13505
X23A-G-003-07
Simultaneous
Display
Bit-Per-Pixel
Option Select
Select Bit 2
Bit 0
Step two involves setting the screen 1 start address registers. Set to 1024 - width for 16 bpp
modes and to (1024 - width) / 2 for 8 bpp modes.
Bit 5
Bit 4
Bit 13
Bit 12
n/a
n/a
Finally set the memory address offset registers to 1024 pixels. In 16 bpp mode load
registers [17h:16h] with 1024 and in 8 bpp mode load the registers with 512.
Bit 5
Bit 4
n/a
n/a
The following limitations apply to SwivelView:
• Only 8/15/16 bpp modes are supported - 1/2/4 bpp modes are not supported.
• Hardware Cursor and Ink Layer images are not rotated - software rotation must be used.
SwivelView must be turned off when the programmer is accessing the Hardware Cursor
or the Ink Layer.
• Split screen images appear side-by-side, i.e. when SwivelView is enabled the screen is
split vertically.
• Pixel panning works vertically.
Bit-Per-Pixel
Bit-Per-Pixel
Select Bit 1
Select Bit 0
Bit 3
Bit 2
Bit 11
Bit 10
Bit 19
Bit 18
Bit 3
Bit 2
n/a
Bit 10
Epson Research and Development
Vancouver Design Center
CRT Enable
LCD Enable
Bit 1
Bit 0
Bit 9
Bit 8
Bit 17
Bit 16
Bit 1
Bit 0
Bit 9
Bit 8
Programming Notes and Examples
Issue Date: 01/02/05
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