Table 7-6: Generic Timing; Vancouver Design Center - Epson S1D13505 Technical Manual

Epson Research and Development

Vancouver Design Center

Symbol
t1
Clock period
t2
Clock pulse width high
t3
Clock pulse width low
A[20:0], M/R# setup to first CLK where CS# = 0 and either
t4
RD0#,RD1#,WE0# or WE1# = 0
A[20:0], M/R# hold from rising edge of either RD0#,RD1#,WE0# or
t5
WE1# = 0
t6
CS# hold from rising edge of either RD0#,RD1#,WE0# or WE1# = 0
1
t7
Falling edge of either RD0#,RD1#,WE0# or WE1# to WAIT# driven low
t8
Rising edge of either RD0#,RD1#,WE0# or WE1# to WAIT# tri-state
D[15:0] setup to third CLK where CS# = 0 and WE0#,WE1# = 0 (write
t9
cycle)
t10
D[15:0] hold (write cycle)
2
t11
Falling edge RD0#,RD1# to D[15:0] driven (read cycle)
t12
D[15:0] setup to rising edge WAIT# (read cycle)
t13
Rising edge of RD0#,RD1# to D[15:0] tri-state (read cycle)
Hardware Functional Specification
Issue Date: 01/02/02

Table 7-6: Generic Timing

Parameter
1. If the S1D13505 host interface is disabled, the timing for WAIT# driven low is relative to the
falling edge of RD0#, RD1#, WE0#, WE1# or the first positive edge of CLK after A[20:0],
M/R# becomes valid, whichever one is later.
2. If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the fall-
ing edge of RD0#, RD1# or the first positive edge of CLK after A[20:0], M/R# becomes valid,
whichever one is later.
3.0V 5.0V
Min Max Min Max
20 20
6 6
6 6
10 10
0 0
0 0
0 15 0 10
5 25 2.5 10
10 10
0 0
0 0
0 0
5 25 5 10
X23A-A-001-14
Page 53
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
S1D13505