Memory Configuration Registers; Table 8-2: Dram Refresh Rate Selection; Vancouver Design Center - Epson S1D13505 Technical Manual

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8.2.2 Memory Configuration Registers

Memory Configuration Register
REG[01h]
Refresh Rate
n/a
Bit 2
bits 6-4
DRAM Refresh Rate
Select Bits [2:0]
000
001
010
011
100
101
110
111
bit 2
bit 0
S1D13505
X23A-A-001-14
Refresh Rate Refresh Rate
Bit 1 Bit 0
DRAM Refresh Rate Select Bits [2:0]
These bits specify the divisor used to generate the DRAM refresh rate from the input clock (CLKI).

Table 8-2: DRAM Refresh Rate Selection

CLKI Frequency
Divisor
64
128
256
512
1024
2048
4096
8192
WE# Control
When this bit = 1, 2-WE# DRAM is selected.
When this bit = 0, 2-CAS# DRAM is selected.
Memory Type
When this bit = 1, FPM-DRAM is selected.
When this bit = 0, EDO-DRAM is selected.
This bit should be changed only when there are no read/write DRAM cycles. This condition occurs
when all of the following are true: the Display FIFO is disabled (REG[23h] bit 7 = 1), and the Half
Frame Buffer is disabled (REG[1Bh] bit 0 = 1), and the Ink/Cursor is inactive
(Reg[27h] bits 7-6 = 00). This condition also occurs when the CRT and LCD enable bits (Reg[0Dh]
bits 1-0) have remained 0 since chip reset. For further programming information, see S1D13505
Programming Notes and Examples, document number X23A-G-003-xx.
n/a WE# Control
Example period for
Example Refresh Rate
256 refresh cycles at
for CLKI = 33MHz
520 kHz
260 kHz
130 kHz
65 kHz
33 kHz
16 kHz
8 kHz
4 kHz
Epson Research and Development

Vancouver Design Center

n/a Memory Type
CLKI = 33MHz
0.5 ms
1 ms
2 ms
4 ms
8 ms
16 ms
32 ms
64 ms
Hardware Functional Specification
Issue Date: 01/02/02
RW