Power Sequencing; Lcd Power Sequencing; Table 7-21: Lcd Panel Power Off/ Power On; Figure 7-22: Lcd Panel Power Off / Power On Timing. Drawn With Lcdpwr Set To Active High Polarity - Epson S1D13505 Technical Manual

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7.4 Power Sequencing

7.4.1 LCD Power Sequencing

SUSPEND# or
LCD Enable Bit
FPFRAME

Figure 7-22: LCD Panel Power Off / Power On Timing. Drawn with LCDPWR set to active high polarity

Symbol
t1
SUSPEND# or LCD ENABLE BIT low to LCDPWR off
t2
SUSPEND# or LCD ENABLE BIT low to FPFRAME inactive
t3
FPFRAME inactive to FPLINE, FPSHIFT, FPDATA, DRDY inactive
t4
SUSPEND# to CLKI inactive
SUSPEND# or LCD ENABLE BIT high to FPLINE, FPSHIFT,
t5
FPDATA, DRDY active
FPLINE, FPSHIFT, FPDATA, DRDY active to LCDPWR, on and
t6
FPFRAME active
t7
CLKI active to SUSPEND# inactive
S1D13505
X23A-A-001-14
t1
LCDPWR
t2
FPLINE
FPSHIFT
FPDATA
DRDY
CLKI

Table 7-21: LCD Panel Power Off/ Power On

Parameter
Note
Where T is the period of FPFRAME and T
FPFRAME
t3
t4
PCLK
Epson Research and Development

Vancouver Design Center

t5 t6
t7
Min Max
2T +
FPFRAME
8T
PCLK
1
128
130
T +
FPFRAME
8T
PCLK
128
0
is the period of the pixel clock.
Hardware Functional Specification
Issue Date: 01/02/02
Units
ns
Frames
Frames
Frames
ns
Frames
ns