Multiple Function Pin Mapping; Table 5-6: Cpu Interface Pin Mapping; Vancouver Design Center - Epson S1D13505 Technical Manual

Page 34

5.4 Multiple Function Pin Mapping

S1D1350
5
SH-3 SH-4
Pin
Names
AB20 A20 A20
AB19 A19 A19
AB18 A18 A18
AB17 A17 A17
AB[16:13] A[16:13] A[16:13] A[16:13]
AB[12:1] A[12:1] A[12:1]
1
AB0 A0 A0
DB[15:8] D[15:8] D[15:8]
DB[7:0] D[7:0] D[7:0]
WE1# WE1# WE1#
M/R#
CS#
BUSCLK CKIO CKIO
BS# BS# BS#
RD/WR# RD/WR# RD/WR#
RD# RD# RD#
WE0# WE0# WE0#
WAIT# WAIT# RDY
RESET# RESET# RESET# RESET#
S1D13505
X23A-A-001-14

Table 5-6: CPU Interface Pin Mapping

MC68K MC68K
Bus 1 Bus 2
A20 A20
A19 A19
A18 A18
A17 A17
A[16:13]
A[12:1] A[12:1]
LDS# A0
D[15:8] D[31:24]
D[7:0] D[23:16]
UDS# DS#
External Decode
External Decode
CLK CLK
AS# AS#
R/W# R/W#
V SIZ1
DD
V SIZ0
DD
DTACK# DSACK1#
RESET# RESET#
Note
1
The bus signal A0 is not used by the S1D13505 internally.
Philips
Generic MIPS/ISA PR31500
/PR31700
A20 LatchA20
A19 SA19 /CARDREG
A18 SA18 /CARDIORD
A17 SA17 /CARDIOWR CARDIOWR*
A[16:13] SA[16:13]
A[12:1] SA[12:1] A[12:1]
1
A0 SA0
D[15:8] SD[15:8] D[31:24]
D[7:0] SD[7:0] D[23:16]
WE1# SBHE# /CARDxCSH
BCLK CLK DCLKOUT
V V
DD DD
RD1# V /CARDxCSL
DD
RD0# MEMR#
WE0# MEMW#
WAIT# IOCHRDY /CARDxWAIT CARDxWAIT*
inverted
RESET#
RESET
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Vancouver Design Center

Toshiba
PowerPC
TX3912
ALE ALE
CARDREG*
CARDIORD*
V V
DD DD
A[12:1]
1 1
A0 A0
D[31:24]
D[23:16]
CARDxCSH*
V
DD
V
DD
DCLKOUT
V V
DD DD
CARDxCSL*
/RD RD*
/WE WE*
PON*
Hardware Functional Specification
PC Card
(PCMCIA)
A11 A20
A12 A19
A13 A18
A14 A17
A[15:18] A[16:13]
A[19:30] A[12:1]
1
A31 A0
D[0:7] D[15:8]
D[8:15 D[7:0]
BI# -CE2
External Decode
External Decode
CLKOUT CLKI
TS# V
DD
RD/WR# -CE1
TSIZ0 -OE
TSIZ1 -WE
TA# -WAIT
inverted
RESET#
RESET
Issue Date: 01/02/02