Host Bus Interface Signal Descriptions - Epson S1D13505 Technical Manual

Epson Research and Development
Vancouver Design Center

3.2 Host Bus Interface Signal Descriptions

Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/05
The S1D13505 PC Card Host Bus Interface requires the following signals.
• BUSCLK is a clock input which is required by the S1D13505 Host Bus Interface. It is
driven by the V832 signal SDCLKOUT.
• The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the V832
address (A[20:0]) and data bus (D[15:0]), respectively. MD4 must be set to select little
endian mode upon reset.
• M/R# (memory/register) selects between memory or register access. It may be
connected to an address line, allowing system address A21 to be connected to the M/R#
line.
• Chip Select (CS#) must be driven low by CSx (where x is the V832 chip select used)
whenever the S1D13505 is accessed by the V832.
• WE1# and RD/WR# connect to LUBEN and LLBEN (the byte enables for the high-
order and low-order bytes). They are driven low when the V832 is accessing the
S1D13505.
• RD# connects to IORD (the read enable signal from the V832).
• WE0# connects to IOWR (the write enable signal from the V832).
• WAIT# is a signal output from the S1D13505 that indicates the V832 must wait until
data is ready (read cycle) or accepted (write cycle) on the host bus. Since V832 accesses
to the S1D13505 may occur asynchronously to the display update, it is possible that
contention may occur in accessing the S1D13505 internal registers and/or display
buffer. The WAIT# line resolves these contentions by forcing the host to wait until the
resource arbitration is complete. For V832 applications, this signal should be set active
low using the MD5 configuration input.
• The Bus Start (BS#) signal is not used for the PC Card Host Bus Interface and should be
tied high (connected to V
• The RESET# (active low) input of the S1D13505 may be connected to the system
RESET.
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