Table 7-18: Fpm-Dram Read/Write/Read-Write Timing; Figure 7-19: Fpm-Dram Read-Write Timing; Vancouver Design Center - Epson S1D13505 Technical Manual

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Memory
Clock
RAS#
CAS#
MA
WE#
MD(read)
MD(write)
Symbol
t1 Internal memory clock period
Random read cycle REG[22h] bit 6-5 == 00
t2 Random read cycle REG[22h] bit 6-5 == 01
Random read cycle REG[22h] bit 6-5 == 10
RAS# precharge time (REG[22h] bits 3-2 = 00)
t3 RAS# precharge time (REG[22h] bits 3-2 = 01)
RAS# precharge time (REG[22h] bits 3-2 = 10)
RAS# to CAS# delay time (REG[22h] bit 4 = 1 and
bits 3-2 = 00 or 10)
RAS# to CAS# delay time (REG[22h] bit 4 = 0 and
bits 3-2 = 00 or 10)
t4
RAS# to CAS# delay time (REG[22h] bit 4 = 1 and
bits 3-2 = 01)
RAS# to CAS# delay time (REG[22h] bit 4 = 0 and
bits 3-2 = 01)
t5 CAS# precharge time
t6 CAS# pulse width
t7 RAS# hold time
Row address setup time (REG[22h] bits 3-2 = 00)
t8 Row address setup time (REG[22h] bits 3-2 = 01)
Row address setup time (REG[22h] bits 3-2 = 10)
S1D13505
X23A-A-001-14
t1
t6
t5
t4
t3
t10 t11
t9
t8
R C2
C1
t12
t14
d1 d2

Figure 7-19: FPM-DRAM Read-Write Timing

Table 7-18: FPM-DRAM Read/Write/Read-Write Timing

Parameter
t1
C3 C1
t21 t16
t15
d3
t18 t19
d1
Min
40
5t1
4t1
3t1
2 t1 - 3
1.45 t1 - 3
1 t1 - 3
1.45 t1 - 3
2.45 t1 - 3
1t1 - 3
2t1 - 3
0.45 t1 - 3
0.45 t1 - 3
0.45 t1 - 3
2 t1 - 3
1.45 t1 - 3
1 t1 - 3
Epson Research and Development

Vancouver Design Center

t7
C2 C3
t17
t20
d2 d3
Max
Hardware Functional Specification
Issue Date: 01/02/02
Units
ns
ns
ns
ns
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