Memory Interface; Table 5-2: Memory Interface Pin Descriptions; Vancouver Design Center - Epson S1D13505 Technical Manual

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5.2.2 Memory Interface

Pin Name Type
LCAS# O 51
UCAS# O 52
WE# O 53
RAS# O 54
34, 36, 38,
40, 42, 44,
46, 48, 49,
MD[15:0] IO
47, 45, 43,
41, 39, 37,
35
Hardware Functional Specification
Issue Date: 01/02/02

Table 5-2: Memory Interface Pin Descriptions

RESET#
Pin # Cell
State
CO1 1
CO1 1
CO1 1
CO1 1
C/TS
Hi-Z
1D
• For dual-CAS# DRAM, this is the column address strobe for the
lower byte (LCAS#).
• For single-CAS# DRAM, this is the column address strobe (CAS#).
See "Memory Interface Pin Mapping" for summary. See Memory
Interface Timing for detailed functionality.
This is a multi-purpose pin:
• For dual-CAS# DRAM, this is the column address strobe for the
upper byte (UCAS#).
• For single-CAS# DRAM, this is the write enable signal for the upper
byte (UWE#).
See "Memory Interface Pin Mapping" for summary. See Memory
Interface Timing for detailed functionality.
• For dual-CAS# DRAM, this is the write enable signal (WE#).
• For single-CAS# DRAM, this is the write enable signal for the lower
byte (LWE#).
See "Memory Interface Pin Mapping" for summary. See Memory
Interface Timing for detailed functionality.
Row address strobe - see Memory Interface Timing for detailed
functionality.
Bi-Directional memory data bus.
During reset, these pins are inputs and their states at the rising edge of
RESET# are used to configure the chip - see Summary of
Configuration Options. Internal pull-down resistors (typical values of
100K at 5V/3.3V respectively) pull the reset states to 0.
External pull-up resistors can be used to pull the reset states to 1.
See Memory Interface Timing for detailed functionality.
Description
X23A-A-001-14
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S1D13505