Table 8-7: Bit-Per-Pixel Selection; Vancouver Design Center - Epson S1D13505 Technical Manual

Epson Research and Development

Vancouver Design Center

bits 4-2
Bit-per-pixel Select Bits [2:0]
bit 1
bit 0
Screen 1 Line Compare Register 0
REG[0Eh]
Screen 1 Line Screen 1 Line
Compare Bit 7 Compare Bit 6
Screen 1 Line Compare Register 1
REG[0Fh]
n/a n/a
REG[0Eh] bits 7-0
REG[0Fh] bits 1-0
Hardware Functional Specification
Issue Date: 01/02/02
Bit-per-pixel Select Bits [2:0]
These bits select the color depth (bpp) for the displayed data. See "Section 10.1 Display Mode For-
mats" for details of how the pixels are mapped into the image buffer.

Table 8-7: Bit-per-pixel Selection

000
001
010
011
100
101
110 – 111
CRT Enable
This bit enables the CRT monitor.
When this bit = 1, the CRT is enabled.
When this bit = 0, the CRT is disabled.
LCD Enable
This bit enables the LCD panel.
Programming this bit from a 0 to a 1 starts the LCD power-on sequence.
Programming this bit from a 1 to a 0 starts the LCD power-off sequence.
Screen 1 Line Screen 1 Line
Compare Bit 5 Compare Bit 4
n/a n/a
Screen 1 Line Compare Bits [9:0]
These bits are set to 1 during power-on.
The display can be split into two images: Screen 1 and Screen 2, with Screen 1 above Screen 2.
This 10-bit value specifies the height of Screen 1.
Height of Screen 1 (lines) = Screen 1 Line Compare Bits [9:0] + 1
If the height of Screen 1 is less than the display height then the remainder of the display is taken up
by Screen 2. For normal operation (no split screen) this register must be set greater than the Vertical
Display Height register (e.g. set to the reset value of 3FFh).
See "Display Configuration" for details.
Color Depth (bpp)
1 bpp
2 bpp
4 bpp
8 bpp
15 bpp
16 bpp
Reserved
Screen 1 Line Screen 1 Line
Compare Bit 3 Compare Bit 2
n/a n/a
Page 107
RW
Screen 1 Line Screen 1 Line
Compare Bit 1 Compare Bit 0
RW
Screen 1 Line Screen 1 Line
Compare Bit 9 Compare Bit 8
S1D13505
X23A-A-001-14