Epson S1D13505 Technical Manual page 507

Epson Research and Development
Vancouver Design Center
Table 3-1: TX3912 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4-1: S1D13505 Configuration for Direct Connection. . . . . . . . . . . . . . . . . . . . . . 12
Table 4-2: TX3912 to PC Card Slots Address Remapping for Direct Connection . . . . . . . . . . 13
Figure 4-1: Typical Implementation of Direct Connection . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5-1: IT8368E Implementation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/05
List of Tables
List of Figures
Page 5
S1D13505
X23A-G-010-04