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3 CPU AND MEMORY CONFIGURATION
In this section, we will explain the CPU and memory configuration.
3.1 CPU
The E0C88832/88862 utilize the E0C88 8-bit core
CPU whose resistor configuration, command set,
etc. are virtually identical to other units in the
family of processors incorporating the E0C88.
See the "E0C88 Core CPU Manual" for the E0C88.
The E0C88832/88862 supports Model 3/minimum
mode of the E0C88 CPU which allows accessing of
the internal memory mapped within the physical
space from 000000H to 00FFFFH.
3.2 Internal Memory
The E0C88832/88862 is equipped with internal
ROM and RAM as shown in Figure 3.2.1.
E0C88832
00FFFFH
I/O memory
00FF00H
00FD42H
Display memory
00F800H
00F7FFH
Unused area
00F600H
00F5FFH
RAM
(1.5K bytes)
00F000H
00EFFFH
Unused area
008000H
007FFFH
ROM
(32K bytes)
000000H
Fig. 3.2.1 Internal memory map
E0C88832/88862 TECHNICAL MANUAL
3.2.1 ROM
The internal ROM capacity is shown in Table
3.2.1.1.
3.2.2 RAM
The internal ROM capacity is shown in Table
3.2.2.1.
E0C88862
I/O memory
3.2.3 I/O memory
Display memory
A memory mapped I/O method is employed in the
E0C88832/88862 for interfacing with internal
Unused area
peripheral circuit. Peripheral circuit control bits and
data register are arranged in data memory space.
RAM
Control and data exchange are conducted via
(1.5K bytes)
normal memory access. The I/O memory is
arranged from address 00FF00H to address
00FFFFH. See Section 5.1, "I/O Memory Map", for
details of the I/O memory.
ROM
(60K bytes)
3.2.4 Display memory
The E0C88832/88862 is equipped with an internal
display memory which stores a display data for
LCD driver.
The display memory is arranged from address
00F800H to address 00FD42H (including the
unused area). See Section 5.11, "LCD Controller",
for details of the display memory.
3.3 Exception Processing Vectors
Address 000000H to address 000023H in the
program area of the E0C88832/88862 is assigned as
exception processing vectors. Furthermore, from
address 000026H to address 0000FFH, software
interrupt vectors are assignable to any two bytes
which begin with an even address.
Table 3.3.1 lists the vector addresses and the
exception processing factors to which they
correspond.
EPSON
3 CPU AND MEMORY CONFIGURATION
Table 3.2.1.1 Internal ROM capacity
Model
ROM capacity
E0C88832
32K bytes
E0C88862
60K bytes
Table 3.2.2.1 Internal ROM capacity
Model
RAM capacity
E0C88832
1.5K bytes
E0C88862
1.5K bytes
Address
000000H–007FFFH
000000H–00EFFFH
Address
00F000H–00F5FFH
00F000H–00F5FFH
13
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