Trap Table Base Register (Ttbr); Arithmetic Operation Registers (Alr And Ahr); Processor Identification Register (Idir); Debug Base Register (Dbbr) - Epson S1C33 Series Core Manual

2 REGISTERS

2.5 Trap Table Base Register (TTBR)

Symbol
TTBR Trap Table Base Register
The Trap Table Base Register (hereinafter referred to as the "TTBR") is a 32-bit register that is used to store the
start address of the vector table to be referenced when an interrupt or exception occurs. During cold reset, the
TTBR is initialized to 0x00C00000*, and the program is executed from the address indicated by the reset vector.
TTBR is a read/writable register, and can be set to any address in the software. However, bits 9–0 in the TTBR are
fixed at 0 and cannot be accessed for writing. Therefore, the addresses that can be set in the TTBR are those that lie
on 1K-byte boundaries.
31
∗ The initial value (0xC00000 by default) can be changed by configuring the hardware parameters.

2.6 Arithmetic Operation Registers (ALR and AHR)

Symbol
ALR Arithmetic Operation Low Register
AHR Arithmetic Operation High Register
One of the special registers included in the C33 PE Core is the arithmetic operation register used in multiply
operations, which consists of the Arithmetic Operation Low Register (hereinafter referred to as the "ALR") and the
Arithmetic Operation High Register (hereinafter referred to as the "AHR"). Each is a 32-bit data register that allows
data to be transferred to and from the general-purpose registers using load instructions. Multiply instructions use
the ALR and the AHR to store the 32 low-order bits and 32 high-order bits of the result of operation, respectively.
When initialized upon reset, the ALR and AHR become indeterminate.

2.7 Processor Identification Register (IDIR)

Symbol
IDIR Processor Identification Register
The Processor Identification Register (hereinafter referred to as the "IDIR") is a 32-bit register that contains the
processor type, revision, and other information. The IDIR is a read-only register, and its readout value varies by
model.
The bit configuration in the IDIR is detailed below.
31
Processor type
Readout value

2.8 Debug Base Register (DBBR)

Symbol
DBBR Debug Base Register
The Debug Base Register (hereinafter referred to as the "DBBR") is a 32-bit register that contains the base address
of a memory area used for debugging. The DBBR is a read-only register which, in the C33 PE Core, is fixed to
0x00060000.
10
Register name
1K-byte boundary address
Figure 2.5.1 Trap Table Base Register (TTBR)
Register name
Register name
24 23
Revision
0x06 Varies by model
Indicates Varies depending on
C33 PE. the processor revision
and installed model.
Figure 2.7.1 Processor Identification Register (IDIR)
Register name
Size
32 bits
10 9
0 0
Size
32 bits
32 bits
Size
32 bits
16 15
Undefined instruction code
Indicates the object code
when an undefined instruction
exception has occurred.
Size
32 bits
EPSON
R/W Initial value
R/W 0x00C00000*
0
0 0 0 0 0 0 0 0
Fixed
(read only)
R/W Initial value
R/W Indeterminate
R/W Indeterminate
R/W Initial value
R 0x06XXXXXX
0xXXXX
R/W Initial value
R 0x00060000
S1C33 FAMILY C33 PE CORE MANUAL
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