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Registers; Register Table; Notes; Functions Of Register Bits (Overview) - Epson RTC-72421 A Applications Manual

Real time clock module
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RTC - 72421 / 72423

Registers

1. Register table

Address
A3
A2
(Hex)
0
0
0
1
0
0
2
0
0
3
0
0
4
0
1
5
0
1
6
0
1
7
0
1
8
1
0
9
1
0
A
1
0
B
1
0
C
1
1
D
1
1
E
1
1
F
1
1

2. Notes

The counts at addresses 0 to C are all positive logic. Therefore, a register bit that is 1 appears as a high-level signal on the data bus.
Data representation is BCD.
Do not set an impossible date or time in the RTC. If such a value is set, the effect is unpredictable.
When the power is turned on (before the RTC is initialized), the state of all bits is undefined. Therefore, write to all registers after
power-on, to set initial values. For details of the initialization procedure, see "Using the RTC-72421/RTC-72423".
The TEST bit of control register F is used by EPSON for testing. Operation cannot be guaranteed if 1 is written to this bit, so make
sure that it is set to 0 during power-on initialization.

3. Functions of register bits (overview)

Bit name
* mark
Not used. Writing to this bit has no effect; reading it always returns 0.
Seconds to year digit
All written BCD code.
This is special (base 7) counter that increments each time the day digits are incremented. It counts from 0 to 6. Since the value in the
counter bears no relationship to the day of the week, the user can choose the coding that relates the counter value to the day of the
week. The following is just one example of this relationship.
Day-of-the-week digit
The PM/AM bit is 1 for p.m. times; 0 for a.m. times. This bit is valid only for 12-hour-clock mode (when the 24/12 bit is 0); in 24-hour-
PM/AM
clock mode (when the 24/12 bit is 1), this bit is always 0.
30-seconds ADJ
Writing 1 to this bit executes a 30-seconds correction.
The IRQ FLAG bit is set to 1 when an interrupt request is generated in fixed-period interrupt mode. Writing 0 to this bit clears it. Note
that it is possible to write 1 to this bit, but this will have no effect.
IRQ FLAG
In fixed-period pulse output mode, this bit is at 1 while the pulse output is active(While the STD.P pin output is low), and is
automatically cleared when pulse output ends. Writing 0 to this bit while pulse output is active forcibly cancels the pulse output.
Use the BUSY bit when accessing data in the S
registers, and is set to 0 otherwise. When the BUSY bit is 1, access to the S
BUSY
Note that the HOLD bit must also be used when accessing the S
There is no need to check the BUSY bit when accessing the control registers (C
When 1 has been written to the HOLD bit, the status of the BUSY bit can be checked. While the HOLD bit is 1, any incrementation of
the digits is held just once. (The incrementation is held only once, even if the HOLD bit remains at 1 for two or more seconds.)
HOLD
Clear the HOLD bit to 0 by forcing the CS1 pin low.
t1,t0
These bits set the timing for fixed-period pulse output and interrupts (1/64 seconds, 1 second, 1minute or 1 hour).
The ITRPT/STND bit sets fixed-period pulse output mode and fixed-period interrupt mode. Write 1 to this bit to set interrupt(INRPT)
ITRPT/STND
mode; when write 0 to it to set pulse output(STND) mode.
The MASK bit disables fixed-period pulse output and fixed-period interrupts. Write 1 to this bit to mask and inhibit these modes; write
MASK
0 to it to enable these modes.
The TEST bit is used by EPSON for test purposes. Operation cannot be guaranteed if 1 is written to this bit, so make sure that it is
TEST
set to 0 during power-on initialization.
The 24/12 bit switches between 24-hour clock and 12-hour clock. Write 1 to this bit to set 24-hour mode; write 0 to it to set 12-hour
24/12
mode. When the 24/12 bit is set, both the timer registers and the timer mode must be reset to match. Note that the h20 bit of the H10
register is always in 12-hour-clock mode.
The STOP bit sets an inhibition on clock operation in 8192 Hz steps which are divisions of the 1 second signal from the RTC's
STOP
internal 32768 Hz oscillation source. The clock is inhibited when the STOP bit is 1, and released again when it becomes 0. The
internal oscillation circuit continues to operate even when the STOP bit is 1.
The RESET bit resets the part of the counter that is below one second. Write 1 to this bit to reset; 0 to release the reset.
RESET
The RESET bit set to 0 when the CS1 pin goes low.
Register
A1
A0
name
D3
0
0
S1
s8
0
1
S10
*
1
0
MI1
mi8
1
1
MI10
*
0
0
H1
h8
0
1
H10
*
1
0
D1
d8
1
1
D10
*
0
0
MO1
mo8
0
1
MO10
*
1
0
Y1
y8
1
1
Y10
y80
0
0
W
*
0
1
CD
30s ADJ
1
0
CE
t1
1
1
CF
TEST
Count
0
Day
Sunday
Monday
Data
D2
D1
s4
s2
s40
s20
mi4
mi2
mi40
mi20
mi10
h4
h2
PM/AM
h20
d4
d2
*
d20
mo4
mo2
*
*
mo10
y4
y2
y40
y20
w4
w2
IRQ FLAG
BUSY
HOLD
ITRPT/
t0
MASK
STND
24/12
STOP
RESET
Function
1
2
3
Tuesday
Wednesday
to W registers. This bit is set to 1 during the incrementation cycle of the S
1
to W registers is inhibited.
1
to W registers. The BUSY bit is always 1 when the HOLD bit is 0.
1
D
Page - 7
Count
(BCD)
D0
s1
0 to 9
1-second digit register
s10
0 to 5
10-seconds digit register
mi1
0 to 9
1-minute digit register
0 to 5
10-minute digit register
h1
0 to 9
1-hour digit register
h10
0 to1 or 2
10-hours digit register
d1
0 to 9
1-day digit register
d10
0 to 3
10-days digit register
mo1
0 to 9
1-month digit register
0 to 1
10-months digit register
y1
0 to 9
1-year digit register
y10
0 to 9
10-years digit register
w1
0 to 6
Day-of-the-week register
Control register D
Control register E
Control register F
4
5
6
Thursday
Friday
Saturday
, C
and C
).
E
F
MQ - 162 - 03
Remarks
to W
1

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