Table 3.7.5 Pin States In Standby Modes - Fujitsu F2MC-8L MB89620 Series Hardware Manual

3.7 Standby Modes (Low-power Consumption)
3.7.5 Pin States in Standby Modes
Table 3.7.5 lists the pin states in standby modes.

Table 3.7.5 Pin States in Standby Modes

Pin name
P00/AD0 to
P07/AD7
P10/A08 to
P17/A15
X0
X1
MOD0
MOD1
RST
P20/BUFC
P21/HAK
P22/HRQ
P23/RDY
P24/CLK
P25/WR
P26/RD
P27/ALE
P30/ADST to
P37/PTO
P40 to
P47/S12
P50/AN0 to
P57/AN7
P60/INT0 to
P63/INT3
P64
*1: Input levels are fixed to prevent leakage by leaving inputs open.
*2: Pin state specification bit (SPL) in the standby control register (STBC)
*3: Operates as a port depending on the external bus pin control register (BCTR) settings.
*4: Pins with a pull-up resistor (optional) go to the pull-up state.
*5: Outputs the write value to the standby control register (STBC).
*6: Outputs the upper address of the standby control register (STBC).
Hi-z: High impedance
Hold: The pin set as output, holds its state (level) immediately before changing to each mode.
Reference: See Appendix E, "MB89620 Series Pin States" for pin states at times other than in a standby
MB89620 series
Sleep mode
Single-chip External bus
mode mode
Data output
Hold
Address
output *6
Oscillator Oscillator
input input
Oscillator Oscillator
output output
Mode input Mode input
Reset input Reset input
"H" output
Hi-z *3
Hi-z
Hold
CLK output
"H" output
"L" output
Hold or Hold or
peripheral I/O peripheral I/O
External External
interrupt input interrupt input
Hi-z *4 Hi-z *4
mode.
Single-chip mode
*2
SPL=0 SPL=1
*5
Hold Hi-z *1,4
*1 *1
Hi-z Hi-z
"H" output "H" output
Mode input Mode input
Reset input Reset input
*3
Hold Hi-z
*1,4
Hi-z
Hold
Hi-z *4
External External
interrupt input interrupt input
Hi-z *4 Hi-z *4
Stop mode
External bus mode
*2 *2
SPL=0 SPL=1
Data output *5
Hi-z *1,4
Address
output *6
*1 *1
Hi-z Hi-z
"H" output "H" output
Mode input Mode input
Reset input Reset input
Hi-z
"H" output *3
Hi-z *1,3 Hi-z *1
Hi-z *1
"L" output
Hi-z
"H" output
"L" output
*1,4
Hi-z
Hold
Hi-z *4
External External
interrupt input interrupt input
Hi-z *4 Hi-z *4
CHAPTER 3 CPU
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