Delta ASDA-B2-F Series User Manual page 164

ASDA-B2-F
0C
0D
0E
0F
P2-50~P2-52 Reserved
P2-53
Operational
Panel / Software
Interface:
Default: 0
Unit: rad/s
Format: DEC
Settings:
When the value of position integral compensation is increased, the position steady-state error is
reduced. However, if the setting value is too big, it may easily cause position overshoot and noise.
P5-54~P2-64 Reserved
P2-65
Operational
Panel / Software
Interface:
Default: 0
Unit: -
Format: -
Settings:
Bit 7
Bit 15

Bit 2 ~ 5, Bit 7 and Bit 14: Reserved (Please set to 0)

Bit 0 ~ Bit 1: Reserved

Bit 6: In DMCNET mode, the switch of pulse error protection function (pulse frequency is too
high)
Bit 6 = 0: Enable the function of pulse error protection
Bit 6 = 1: Disable the function of pulse error protection

Bit 8: Reserved

Bit 9: U, V, W wiring cut-off detection
Bit 9 = 1: Enable U, V, W wiring cut-off detection

Bit 10: Reserved

Bit 12: Phase loss detection
Bit12 = 0: Enable phase loss (AL022) detection
Bit12 = 1: Disable phase loss (AL022) detection

Bit13: Encoder output error detection function
Bit13 = 0: Enable encoder output error (AL018) detection function
Bit13 = 1: Disable encoder output error (AL018) detection function

Bit15: Friction compensation mode selection
Bit15 = 0: If the speed is slower than the value of P1-38, the compensation value remains.
Bit15 = 1: If the speed is slower than the value of P1-38, the compensation value becomes 0.
September, 2015
950
900
850
800
KPI Position Integral Compensation
Communication
GBIT Special-bit Register
Communication
Bit 6 Bit 5 Bit 4
Bit 14 Bit 13 Bit 12
1C 175
1D 150
1E 125
1F 100
Address: 026AH
Related
-
Section:
Control
ALL
Mode:
Range: 0 ~ 1023
Data Size: 16-bit
Address: 0282H
Related
-
Section:
Control
DMCNET / Sz
Mode:
Range: 0 ~ 0xFFFF
Data Size: -
Bit 3 Bit 2 Bit 1
Bit 11 Bit 10 Bit 9
Parameters
7
026BH
0283H
Bit 0
Bit 8
7-47