The Instruction Pipeline; Instruction Processing; Table 6-35 Data Alu Instructions-Dual Parallel Read - Motorola DSP56800 Manual

Instruction Set Introduction
For the MAC, MPY, MACR, and MPYR instructions, the assembler accepts the two source operands in
any order.
Table 6-35. Data ALU Instructions—Dual Parallel Read
Data ALU
Operation
Operation Operands
MAC Y1,X0,F
MPY Y1,Y0,F
MACR Y0,X0,F
MPYR
ADD X0,F
SUB Y1,F
Y0,F
MOVE
Each instruction in Table 6-35 requires one program word and executes in one cycle.
The data types accessed by the two memory moves in all dual parallel read instructions are signed words.
6.7

The Instruction Pipeline

Instruction execution is pipelined to allow most instructions to execute at a rate of one instruction every
two clock cycles. However, certain instructions require additional time to execute, including instructions
with the following properties:
• Exceed length of one word
• Use an addressing mode that requires more than one cycle
• Access the program memory
• Cause a control flow change
In the case of a control flow change, a cycle is needed to clear the pipeline.
6.7.1

Instruction Processing

Pipelining allows the fetch-decode-execute operations of an instruction to occur during the
fetch-decode-execute operations of other instructions. While an instruction is executed, the next instruction
to be executed is decoded, and the instruction to follow the instruction being decoded is fetched from
program memory. If an instruction is two words in length, the additional word will be fetched before the
next instruction is fetched.
Figure 6-4 demonstrates pipelining; F1, D1, and E1 refer to the fetch, decode, and execute operations,
respectively, of the first instruction. Note that the third instruction contains an instruction extension word
and takes two cycles to execute.
6-30
First Memory
Read
Source 1 Destination 1
X:(R0)+ Y0
X:(R0)+N Y1
X:(R1)+
X:(R1)+N
DSP56800 Family Manual
Second Memory
Read
Source 2 Destination 2
X:(R3)+ X0
X:(R3)-