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SECTION 7
P
PC ARCHITECTURE COMPLIANCE
OWER
This section describes implementation-dependent choices made for the core on issues that
™
architecture as defined in the PowerPC Architecture Books
are optional on the PowerPC
I, II, and III . It also describes features that exist in the architecture, but are not supported by
the core. The information in this section is based on the PowerPC books, but you can also
refer to the PowerPC Microprocessor Family: The Programming Environment for 32-Bit
Microprocessors (MPCFPE32B/AD) manual for more information.
7.1 P
PC USER INSTRUCTION SET ARCHITECTURE (BOOK I)
OWER
7.1.1 Computation Modes
The core is a 32-bit fixed-point implementation of the PowerPC architecture. Any reference
in the PowerPC Architecture Books I, II, and III regarding 64-bit implementations are not
supported by this core. No floating point of the architecture is implemented.
7.1.2 Reserved Fields
Reserved fields in instructions are described under the specific instruction definition
sections. Unless otherwise stated in the specific instruction description, fields marked
I, II, and III in the instruction are discarded by the core decoding. Thus, this type of invalid
form instructions yield results of the defined instructions with the appropriate field zero. In
most cases, the reserved fields in registers are ignored on write and return zeros for them
on read for any control register implemented by the core. Exceptions to this rule are bits
16-23 of the fixed-point exception cause register (XER) and the reserved bits of the machine
state register (MSR), which are set by the source value on write and return the value last set
for it on read.
7.1.3 Classes of Instructions
Nonoptional instructions (except floating-point load, store, and compute instructions) are
implemented by the hardware. Optional instructions are executed by
implementation-dependent code and any attempt to execute one of these commands
causes the core to take the implementation-dependent software emulation interrupt (offset
x'01000' of the vector table). Illegal and reserved instruction class instructions are supported
by implementation-dependent code and, thus the core hardware generates the
implementation-dependent software emulation interrupt. How the core treats invalid and
preferred instruction forms is described in the specific processor compliance sections.
MOTOROLA
MPC823e REFERENCE MANUAL
7-1
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