Instruction Set - Motorola CPU32 Reference Manual

1.1.6 Instruction Set
The instruction set of the CPU32 is very similar to that of the MC68020 (see
Table 1-1). Two new instructions have been added to facilitate controller
applications - low-power stop (LPSTOP) and table lookup and interpolate
(TBL). The following M68020 instructions are not implemented on the
CPU32:
BFxxx - Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO,
BFINS, BFSET, BFTST)
CALLM, RTM - Call Module, Return Module
CAS, CAS2 - Compare and Set (Read-Modify-Write Instructions)
cpxxx - Coprocessor Instructions (cpBcc, cpDBcc, cpGEN, cpRESTORE,
cpSAVE, cpScc, cpTRAPcc)
PACK, UNPK - Pack, Unpack BCD Instructions
The CPU32 traps on unimplemented instructions and illegal effective
addressing modes, allowing the user to emulate instructions or to define
special-purpose functions. However, Motorola reserves the right to use all
currently unimplemented instruction operation codes for future M68000 core
enhancements.
See SECTION 4 INSTRUCTION SET for comprehensive information.
1.1.6.1 Table Lookup and Interpolation Instructions
To speed up real-time applications, a range of discrete data points is often
precalculated from a continuous control function, then stored in memory. A full
range of data can require an inordinate amount of memory. The table
instructions make it possible to store a sample of the full range and recover
intermediate values quickly via linear interpolation. A round-to-nearest
algorithm can be applied to the results.
CPU32 REFERENCE MANUAL OVERVIEW MOTOROLA
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