Introduction - Analog Devices VisualDSP++ 5.0 Service Manual

Introduction

Introduction
The Blackfin processor employs a two-tiered mechanism for controlling
interrupts and events. System-level interrupts are controlled by the system
interrupt controller (SIC). All peripheral interrupt signals are routed
through the system interrupt controller and then, depending on the set-
tings of the system interrupt controller, routed to the core event controller
(CEC). The core event controller processes these events and, depending
on the settings of the core event controller, vectors the processor to handle
the events.
The interrupt manager provides functions that allow the application to
control every aspect of the system interrupt controller and the core event
controller. It does this so that events and interrupts are handled and pro-
cessed in an efficient, yet cooperative, manner.
The Blackfin processor provides 16 levels of interrupt and events. These
levels, called interrupt vector groups (IVG), are numbered from 0 to 15,
with the lowest number having the highest priority. Some IVG levels are
dedicated to certain events, such as emulation, reset, non-maskable inter-
rupt (NMI, and so on. Other IVG levels, specifically levels 7 through 15,
are considered general-purpose events and are typically used for system-
level (peripheral) interrupts or software interrupts.
All IVG processing is performed in the CEC. When a specific IVG is trig-
gered, assuming the event is enabled, the CEC looks up the appropriate
entry in the event vector table and vectors execution to the address in the
table where the event is processed.
All system or peripheral interrupts are first routed through the SIC.
Assuming the SIC has been programmed, peripheral interrupts are then
routed to the CEC for processing. The SIC provides a rich set of function-
ality for the processing and handling of peripheral interrupts. In addition
to allowing/disallowing peripheral interrupts to be routed to the CEC, the
2-2 VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors