Adi_Pwr_Df; Adi_Pwr_Input_Delay; Adi_Pwr_Output_Delay - Analog Devices VisualDSP++ 5.0 Service Manual

Public Data Types and Enumerations

ADI_PWR_DF

This data type defines the values for the
A value of
ADI_PWR_DF_ON
PLL module. According to the ADSP-BF533 Blackfin Processor Hardware
Reference, this leads to lower power dissipation
ADI_PWR_DF_NONE
ADI_PWR_DF_OFF
ADI_PWR_DF_ON

ADI_PWR_INPUT_DELAY

This data type defines the values that the input delay bit can take in the
PLL control register.
ADI_PWR_INPUT_DELAY_DISABLE
ADI_PWR_INPUT_DELAY_ENABLE

ADI_PWR_OUTPUT_DELAY

This data type defines the values that the output delay bit can take in the
PLL control register.
ADI_PWR_OUTPUT_DELAY_DISABLE
ADI_PWR_OUTPUT_DELAY_ENABLE
1
See ADSP-BF533 Blackfin Processor Hardware Reference, Revision 3.2, July 2006, page 8-4.
3-48
bit in the PLL control register.
DF
causes the value of
Indicates that no PLL input divider value is to be set.
Pass to the PLL.
CLKIN
Pass to the PLL.
CLKIN/2
Do not add input delay.
Add approximately 200 ps of delay to the time when
inputs are latched on the external memory interface.
Do not add output delay.
Add approximately 200 ps of delay to external
memory output signals.
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
to be passed to the
CLKIN/2
1
.