Analog Devices VisualDSP++ 5.0 Service Manual page 199

Table 4-3. ADI_EBIU_COMMAND Data Values (Cont'd)
Command
ADI_EBIU_CMD_SET_SDRAM_PASR
ADI_EBIU_CMD_SET_SDRAM_TCSR
ADI_EBIU_CMD_SET_SDRAM_SCTLE
ADI_EBIU_CMD_SET_DDR_DATA_WIDTH
ADI_EBIU_CMD_SET_DDR_EXTERNAL_BANKS
ADI_EBIU_CMD_SET_DDR_DEVICE_WIDTH
ADI_EBIU_CMD_SET_DDR_DEVICE_SIZE
ADI_EBIU_CMD_SET_DDR_REFI
ADI_EBIU_CMD_SET_DDR_RFC
ADI_EBIU_CMD_SET_DDR_CAS
ADI_EBIU_CMD_SET_DDR_RCD
ADI_EBIU_CMD_SET_DDR_RC
ADI_EBIU_CMD_SET_DDR_RAS
ADI_EBIU_CMD_SET_DDR_RP
ADI_EBIU_CMD_SET_DDR_MRD
ADI_EBIU_CMD_SET_DDR_WTR
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
External Bus Interface Unit Module
Associated Data Value
ADI_EBIU_SDRAM_PASR
banks are refreshed. Applicable only to low power
SDRAM. See
"ADI_EBIU_CMD_SET_SDRAM_SCTLE" on
page 4-40.
ADI_EBIU_SDRAM_TCSR
temperature-compensated, self-refresh value.
This command can only be used for low power
SDRAM. See "ADI_EBIU_SDRAM_PASR" on
page 4-41.
ADI_EBIU_SDRAM_SCTLE
whether the SDC is enabled. See
"ADI_EBIU_CMD_SET_SDRAM_SCTLE" on
page 4-40.
Set DDR width of data
Set number of DDR external banks
Set DDR width of device
Set size of device
Set DDR auto-refresh interval
Set auto-refresh command period
Set DDR CAS latency: cycles from R/W to first
valid data
Set interval between active command and R/W
assertion
Set interval between successive DDR activate
commands
Set DDR active to precharge interval
Set DDR precharge to active interval
Set DDR interval between setting of mode
register and next command
Set DDR interval between write and read
command
value specifying which
value specifying the
value specifying
4-35