Synchronization Between Cores; Built-In Lock Variable And Linking Considerations - Analog Devices VisualDSP++ 5.0 Service Manual

Dual-Core Considerations

Synchronization Between Cores

Either core can interrupt the other core using a supplemental interrupt.
There are two of these on the ADSP-BF561 processor: 0 and 1. A shared
lock variable located in L2 memory can send information between the
cores as a method of synchronization.
The built-in mechanism requires that core A initiates all power manage-
ment changes, with core B configured to respond to a supplemental
interrupt 0 event, raised by core A. The configuration and handling of this
interrupt is managed within the power management module itself.
Table 3-2 describes the synchronization sequence.
Table 3-2. Synchronization Sequence Between Cores
Core A
Raises supplemental interrupt 0, sets the shared
adi_pwr_lockvar lock variable, and waits
acknowledgement.
On receiving acknowledgement, performs PLL
programming sequence, and configures the SDC
accordingly.
Completes the process by clearing the lock vari-
able.

Built-In Lock Variable and Linking Considerations

The lock variable,
fin\lib\src\ services\pwr\adi_pwr_lockvar.c
section ("l2_shared") testset_t adi_pwr_lockvar = 0;
where the memory input section,
output section in both the default and generated linker
MEM_L2_SRAM
description files (
3-10
adi_pwr_lockvar
l2_shared
).
.ldf
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
Core B
Responds to supplemental interrupt 0 by
entering interrupt handler.
Runs first (optional) callback function.
Acknowledges interrupt and goes to IDLE.
Wakes on PLL wakeup and waits for the
lock variable to clear.
Runs second (optional) callback function,
and returns from interrupt.
, is declared within the file
as:
, is mapped to the
Black-