Analog Devices VisualDSP++ 5.0 Service Manual page 172

Using the EBIU Module
In the sample code above, note that the SDRAM minimum
defined as a structure called
main parts: a number of cycles, and a number of timing units, in this case,
picoseconds. This representation reflects the definition found in the
appropriate SDRAM data sheet where the value is expressed as one cycle
of plus 7.5 ns. For the SDRAM refresh period, this structure
SCLK
expresses the time taken for the given number of refresh cycles. The sam-
ple code shows that the refresh period is 64 milliseconds, which takes
8192 cycles.
For hardware that uses a Micron SDRAM module, the command-pair
table can be abbreviated to just specify the type of the module and the size
of the bank, as shown below, adding asynchronous memory controller
commands, as needed:
ADI_EBIU_SDRAM_BANK_VALUE bank_size;
// set bank size to 32MB
bank_size.value.size = ADI_EBIU_SDRAM_BANK_32MB;
ADI_EBIU_COMMAND_PAIR ebiu_init_table[] = {
// MT48LC16M16-75 module
{ ADI_EBIU_CMD_SET_SDRAM_MODULE,
(void*)ADI_EBIU_SDRAM_MODULE_MT48LC16M16A2_75 },
{ ADI_EBIU_CMD_SET_SDRAM_BANK_SIZE, (void*)&bank_size },
{ ADI_EBIU_CMD_END, 0 }
};
adi_ebiu_Init(ebiu_init_table, 0);
4-8
ADI_EBIU_TIMING_VALUE
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
value is
TWR
which consists of two