Analog Devices VisualDSP++ 5.0 Service Manual page 170

Using the EBIU Module
To illustrate what is required for Blackfin processors that support DDR
memory, a command table is shown below. Replace the SDRAM parame-
ters, above, with the DDR parameters shown below, and add the
asynchronous memory controller commands shown in the above example.
ADI_EBIU_TIMING_VALUE RC
ADI_EBIU_TIMING_UNIT_NANOSEC
active command and the next */
ADI_EBIU_TIMING_VALUE RAS =
ADI_EBIU_TIMING_UNIT_NANOSEC
command and precharge command */
ADI_EBIU_TIMING_VALUE RP =
ADI_EBIU_TIMING_UNIT_NANOSEC
precharge command and active command */
ADI_EBIU_TIMING_VALUE RFC =
ADI_EBIU_TIMING_UNIT_NANOSEC
recover from REFRESH signal */
ADI_EBIU_TIMING_VALUE WTR =
{7500,ADI_EBIU_TIMING_UNIT_PICOSEC }}; /* cycles from last write
data until next read command */
ADI_EBIU_TIMING_VALUE tWR =
ADI_EBIU_TIMING_UNIT_NANOSEC
2 or 3 cycles */
ADI_EBIU_TIMING_VALUE tMRD =
ADI_EBIU_TIMING_UNIT_NANOSEC }};
mode */
ADI_EBIU_TIMING_VALUE RCD =
ADI_EBIU_TIMING_UNIT_NANOSEC
command to next R/W */
ADI_EBIU_TIMING_VALUE REFI =
ADI_EBIU_TIMING_UNIT_NANOSEC}};
signal to the next */
4-6
{ 8, {60,
}}; /* cycles between one
{ 6, {42,
}}; /* cycles between active
{ 2, {15,
}}; /* cycles between
{ 10,{72,
}}; /* cycles for SDRAM to
{ 2,
{ 2, {15,
}}; /* write recovery time is
{ 2, {15,
/* cycles from setting of
{ 2, {15,
}}; /* cycles from active
{ 1037,{7777,
/* cycles from one REFRESH
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors