Adi_Ebiu_Asynch_Bank_Ardy_Enable; Adi_Ebiu_Asynch_Bank_Ardy_Polarity; Adi_Ebiu_Asynch_Hold_Time - Analog Devices VisualDSP++ 5.0 Service Manual

Setting Control Values in the EBIU Module

ADI_EBIU_ASYNCH_BANK_ARDY_ENABLE

Each asynchronous bank can be programmed to sample the
which allows the bank access time to be extended. Sampling the
determines how long to extend the access time. This enumeration specifies
whether or not the
bit (where
BXRDYEN
bank control 0 register (for banks 0 and 1) or the asynchronous memory
bank control 1 register (for banks 2 and 3).
ADI_EBIU_ASYNCH_ARDY_DISABLE
ADI_EBIU_ASYNCH_ARDY_ENABLE

ADI_EBIU_ASYNCH_BANK_ARDY_POLARITY

This enumeration specifies, if
complete when the
bit (where
BXRDYPOL
bank control 0 register (for banks 0 and 1) or the asynchronous memory
bank control 1 register (for banks 2 and 3).
ADI_EBIU_ASYNCH_ARDY_POLARITY_LOW
ADI_EBIU_ASYNCH_ARDY_POLARITY_HIGH

ADI_EBIU_ASYNCH_HOLD_TIME

The hold time for the asynchronous memory controller is specified in the
field of an
bank_time
ture. That field is of type "ADI_EBIU_TIMING_VALUE", which in this
case can either specify a number of cycles or an
value, but not both. When cycles are used, the
ADI_EBIU_ASYNCH_HOLD_TIME
of hold time. It corresponds to the
in the asynchronous memory bank control 0 register (for banks 0 and 1)
or the asynchronous memory bank control 1 register (for banks 2 and 3).
4-46
signal will be sampled. It corresponds to the
ARDY
is the bank number) in the asynchronous memory
X
Sampling of
Sampling of
is enabled, whether the access time is
ARDY
signal is low or high. It corresponds to the
ARDY
is the bank number) in the asynchronous memory
X
Transaction is complete if
Transaction is complete if
"ADI_EBIU_ASYNCH_BANK_TIMING"
enumeration specifies the number of cycles
BXHT
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
is disabled.
ARDY
is enabled.
ARDY
ARDY
ARDY
"ADI_EBIU_TIME"
bit (where is the bank number)
X
input,
ARDY
pin
ARDY
is low.
is high.
struc-