Using the Port Control Manager
To demonstrate the use of the port control manager, an example is
presented that configures the PPI for use with two internal frame syncs.
The port control manager is initialized as follows.
adi_ports_Init(
NULL
);
To enable the flag pins for the required PPI use, the
function is called with an array of directives that determine how to config-
ure the register.
// Configure the PPI_CONTROL register
ADI_PPI_CONTROL_REG ppi_control;
ppi_control.port_en
ppi_control.port_dir = 0;
ppi_control.xfr_type = 3;
ppi_control.port_cfg = 1;
ppi_control.dlen
ppi_control.polc
ppi_control.pols
// set PPI_COUNT to 1 to sample 2 16-bit words.
u16 ppi_count = 1;
u16 ppi_frame = 1;
ADI_DEV_CMD_VALUE_PAIR PPI_config[] = {
{ ADI_PPI_CMD_SET_CONTROL_REG, (void*)(*(u16*)&ppi_control)
{ ADI_PPI_CMD_SET_TRANSFER_COUNT_REG, (void*)(*(u16*)&ppi_count)
},
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
// Initialize Port Control Manager
// No special data area for critical
// regions required
= 0;
// Disable until ready
// Receive mode
// Non ITU-R 656 mode
// two or three internal frame syncs
= 7;
// 16 Bits data length
= 0;
// Do not invert PPI_CLK
= 0;
// Do not invert PPI_FS1 & PPI_FS2
Port Control Service
adi_ports_EnablePPI
},
9-3
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