Analog Devices VisualDSP++ 5.0 Service Manual page 155

Visualdsp++ 5.0 device drivers and system for blackfin processors
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Table 3-7. PM Module Return Values (Cont'd)
Return Value
ADI_PWR_RESULT_NOT_INITIALIZED
ADI_PWR_RESULT_ALREADY_INITIALIZED
ADI_PWR_RESULT_INVALID_VDDEXT
ADI_PWR_RESULT_INVALID_PROCESSOR
ADI_PWR_RESULT_INVALID_IVG
ADI_PWR_RESULT_INVALID_INPUT_DELAY
ADI_PWR_RESULT_INVALID_OUTPUT_DELAY
ADI_PWR_RESULT_INVALID_LOCKCNT
ADI_PWR_RESULT_INVALID_MODE
ADI_PWR_RESULT_INVALID_CSEL
ADI_PWR_RESULT_INVALID_SSEL
ADI_PWR_INVALID_CSEL_SSEL_COMBINATION
ADI_PWR_RESULT_VOLTAGE_REGULATOR_BYPASSED
ADI_PWR_RESULT_INVALID_VR_VLEV
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
Power Management Module
Explanation
Function call has been ignored with
no action taken, due to the PM
module not being initialized.
A call to
adi_pwr_Init
ignored with no action taken, due
to the PM module having already
been initialized.
Invalid external voltage level has
been specified.
Processor type specified is invalid.
IVG level supplied for PLL wakeup
is invalid.
Input delay value is invalid.
Output delay value is invalid.
PLL lock count value is invalid.
Invalid operating mode has been
specified.
Invalid value for
specified.
Invalid value for
specified.
Core clock divider is greater that
the system clock divider value, or
both
ADI_PWR_CSEL_NONE
ADI_PWR_SSEL_NONE
Voltage regulator cannot be set
since it is in bypass mode.
argument is invalid or insuffi-
VLEV
cient to sustain the current core and
system clock frequencies.
has been
has been
CSEL
has been
SSEL
and
are specified.
3-51

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