Adi_Ebiu_Sdram_Psm; Adi_Ebiu_Sdram_Fbbrw - Analog Devices VisualDSP++ 5.0 Service Manual

The default value is specified by the following macro:
#define ADI_EBIU_SDRAM_PUPSD_DEFAULT
ADI_EBIU_SDRAM_PUPSD_NODELAY

ADI_EBIU_SDRAM_PSM

This enumeration specifies the SDRAM power-up sequence. This enu-
meration corresponds to the
ADI_EBIU_SDRAM_PSM_REFRESH_FIRST
ADI_EBIU_SDRAM_PSM_REFRESH_LAST
The default value is specified by the following macro:
#define ADI_EBIU_SDRAM_PSM_DEFAULT
ADI_EBIU_SDRAM_PSM_REFRESH_FIRST

ADI_EBIU_SDRAM_FBBRW

This enumeration specifies whether the EBIU uses fast back-to-back,
read-write access to allow SDRAM read and write operations on
consecutive cycles. This enumeration corresponds to the
register.
EBIU_SDGCTL
ADI_EBIU_SDRAM_FBBRW_DISABLE
ADI_EBIU_SDRAM_FBBRW_ENABLE
The default value is specified by the following macro:
#define ADI_EBIU_SDRAM_FBBRW_DEFAULT
ADI_EBIU_SDRAM_FBBRW_DISABLE
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
External Bus Interface Unit Module
bit in the
PSM EBIU_SDGCTL
SDC performs a
lowed by eight auto-refresh cycles, and then a
Mode Register
SDC performs a
lowed by a
Load Mode Register
then completes eight auto-refresh cycles.
Fast back-to-back, read-write access disabled.
SDRAM read and write operations occur on
consecutive cycles.
register.
command, fol-
Precharge All
command.
command, fol-
Precharge All
command, and
bit in the
FBBRW
Load
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