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FEATURES
Measures Battery Stack Voltage, Current and Power
n
Indicates Accumulated Battery Charge and Energy
n
20-Bit Current Measurement with <1μV Offset
n
Built-In Isolated isoSPI™ or SPI Interface
n
LTC68xx/ADBMS68xx Compatible, Supports
n
Synchronous Measurements with Cell Monitors
Up to 12 Buffered Voltage Measurement Inputs
n
Up to 5 GPIOs, Configurable to Drive Ground, Supply
n
or Toggling at 400kHz
High or Low Side Current Sense
n
0.3% Current and Voltage Accuracy
n
1% Energy and Charge Accuracy
n
True Average ADCs
n
2
I
C EEPROM Interface to Store Board Calibration Factors
n
Threshold Registers for all Measured Quantities
n
Engineered for ISO26262 Compliant Systems
n
Open Wire Detection on Input Pins
n
Available in 48-Lead LQFP Package
n
AEC-Q100 Qualified for Automotive Applications
n
APPLICATIONS
Electric and Hybrid Vehicles
n
Isolated Current Sensing
n
Backup Battery Systems
n
High Power Portable Equipment
n
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
+
HV
800V
BAT
isoSPI B
isoSPI A
CELL
MONITORS
isoSPI B
isoSPI A
–
HV
BAT
Document Feedback
Current, Voltage, and Charge Monitor for
Electric Vehicle Battery Meter
3.3M
ISOLATION
RESISTANCE
LT830x
3.3M
6.5M
6.5M
STACK
30k
30k
VOLTAGE
MASTER
LTC6820
SPI
SPI
isoSPI
GND
GND
ISOLATED COMMUNICATION
For more information
High Voltage Battery Packs
DESCRIPTION
The
LTC
2949
is a high precision current, voltage, tem-
®
perature, charge and energy meter for electrical and hybrid
vehicles and other isolated current sense applications. It
infers charge and energy flowing in and out of the battery
pack by monitoring simultaneously the voltage drop over
up to two sense resistors and the battery pack voltage.
Low offset ΔΣ ADCs ensure accurate measurement of
voltage and current with insignificant power loss. Con-
tinuous integration of current and power ensures lossless
tracking of charge and energy delivered or received by
the battery pack.
The built-in serial interface can be configured to support
isolated isoSPI communication to the host or as SPI
interface.
The LTC2949 features 12 internally buffered high imped-
ance inputs (V1 to V12) for measuring voltages from
external sensors or resistor dividers allowing to measure
temperatures, HV-Link voltages, chassis isolation and
supervise contactor states. LTC2949 has up to five pro-
grammable digital outputs which can be set to ground,
supply or toggling at 400kHz.
Programmable threshold and tracking registers reduce
digital traffic to the host.
AVCC
DVCC
LTC2949
1µF
V5
GND
30k
V4
GPIO1
VREF
V1
BATP
POWER
ENERGY
V3
BATM
V2
CURRENT
CHARGE
isoSPI
I1P
I1M
I2P
I2M
50µ
www.analog.com
LTC2949
+
HV
LINK
6.5M
LINK VOLTAGE
22k
100k
22k
LINK VOLTAGE
TEMPERATURE
6.5M
100k
–
HV
LINK
2949 TA01
Rev A
1
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Related Manuals for Analog Devices LTC2949
Summary of Contents for Analog Devices LTC2949
-
Page 1: Features
AEC-Q100 Qualified for Automotive Applications temperatures, HV-Link voltages, chassis isolation and APPLICATIONS supervise contactor states. LTC2949 has up to five pro- grammable digital outputs which can be set to ground, Electric and Hybrid Vehicles supply or toggling at 400kHz. -
Page 2: Table Of Contents
Register Map PAGE1 ............................62 Application Information ......................68 Temperature Measurement ..........................68 Sense Resistor Temperature Compensation ......................69 Current and Voltage Input Filtering ........................74 Powering the LTC2949 ............................75 Package Description ......................78 Revision History .........................79 Typical Application ......................80 Related Parts ........................80... -
Page 3: Absolute Maximum Ratings
#3ZZ suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. -
Page 4: Electrical Characteristics
LTC2949 ELECTRICAL CHARACTERISTICS denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. SYMBOL PARAMETER CONDITIONS UNITS Power Supply Analog Supply Voltage AVCC Digital Supply Voltage DVCC Supply Undervoltage Lockout Threshold Falling... - Page 5 LTC2949 ELECTRICAL CHARACTERISTICS denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. SYMBOL PARAMETER CONDITIONS UNITS Input Voltage Common Mode Rejection at DC Input Sampling Frequency 10.48 Conversion Time Slow Mode Filtered...
- Page 6 LTC2949 ELECTRICAL CHARACTERISTICS denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. SYMBOL PARAMETER CONDITIONS UNITS Energy Measurement Energy Total Unadjusted Error 1V ≤ |VDIF | ≤ 4.8V, 25mV ≤ |VDIF | ≤...
- Page 7 LTC2949 ELECTRICAL CHARACTERISTICS denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. SYMBOL PARAMETER CONDITIONS UNITS Pull-Up Current Source Pin Voltage < V − 3.0V –250 –150 µA AVCC Pull-Down Current Source Pin Voltage >...
- Page 8 LTC2949 ELECTRICAL CHARACTERISTICS denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. SYMBOL PARAMETER CONDITIONS UNITS SCK Low ≥ 1μs SCK High ≥ 1μs CSB Rising Edge to CSB Falling Edge 0.65...
- Page 9 LTC2949 ELECTRICAL CHARACTERISTICS denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. SYMBOL PARAMETER CONDITIONS UNITS C Interface Timing Specification (SCL, SDA) Maximum SCL Clock Frequency SCL(MAX) SCL Low Period µs...
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Page 10: Typical Performance Characteristics
LTC2949 TYPICAL PERFORMANCE CHARACTERISTICS Current Measurement Gain Error Current Measurement Offset Current Measurement Offset Current Measurement Current Measurement Current Measurement Offset vs Temperature vs Temperature Distribution Gain Error vs Temperature Offset vs Temperature Distribution 0.20 12 Randomly Chosen Demo Boards 0.15... -
Page 11: Pin Functions
BYP2 to DGND with a 1μF capacitor. Can supply external range is 4.5V to 14V. circuitry (example SPI isolator ADuM141E or ADuM4154) with up to 10mA. Overloading might disrupt LTC2949 AGND (Pin 18): Analog Ground. Bypass this pin to AVCC functionality. -
Page 12: Pin Functions
LTC2949 PIN FUNCTIONS CF2P , CF2M (Pins 39, 40): Filter Capacitor Inputs for the prevents LTC2949 to go automatically into SLEEP state and second current channel. Connect a 1µF capacitor between to execute HW memory BIST. Connect a 4.7k-10k pull-up... -
Page 13: Block Diagram
LTC2949 BLOCK DIAGRAM DEGLITCH FILTER OCC1 STATUS CF1P CONTROL 18 BIT, 100ms SLOW CURRENT 1 THRESHOLDS 15 BIT, 0.78ms FAST CURRENT 1 CURRENT 1 TRACKING CF1M P or V 18 BIT, 100ms POWER 1 THRESHOLDS SLOW 15 BIT, 0.78ms VBATP... -
Page 14: Operation
LTC2949 OPERATION OVERVIEW measured in slow mode, and the LTC2949 will set the corresponding bit in the Alert Register if a threshold is The LTC2949 is a high precision current, voltage, charge exceeded. Programmable heartbeat functions on up to two... -
Page 15: Modes Of Operation
MEASURE state by setting the single shot (SSHOT) or poll the SLEEP bit in the Operation Control Register to check continuous (CONT) bit in the Operations Control Register that the LTC2949 is awake and in STANDBY mode (see also OPCTRL. Figure 20 about Wake-Up and Boot procedure). LTC2949... -
Page 16: Data Acquisition Channels
NO ACTIVITY ON IDLE TRANSMIT/RECEIVE isoSPI PORT to the LTC2949 core is only possible if the isoSPI port is not in IDLE state. This means that even when the LTC2949 core is in STANDBY or MEASURE state and the isoSPI port ACTIVE is in IDLE state, communication can only take place 10µs... - Page 17 SSHOT, sets the bit The LTC2949 provides a fast mode with a reduced conver- UPDATE in Status Register and returns to the STANDBY sion time of 782µs and a resolution of 15-bit. Fast mode state.
- Page 18 In a typical application case, both data acquisition channels PasV=1), otherwise, the power ADC result is 0. If both offered by LTC2949 could monitor the current over a single channels are in fast mode with their power ADCs in volt- shunt resistor, where CH1 is used to do high precision age mode, BAT is obtained from PADC1.
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Page 19: Power Measurement
CONT in OPCTRL. peak current is drawn. The scheme used by the LTC2949 Conversions on CH1 and CH2 take 100ms and a new RR avoids this error, maintaining specified accuracy with cycle of CHAUX is started at every start of conversion of CH1. -
Page 20: Charge, Energy And Time
It also keeps track of total accumulated time 2949 F05 used for the integration. 33pF 33pF For the quantities charge and energy the LTC2949 provides three sets of registers each, for the quantity "time" four register sets. X1: ABLS2-4.000MHZ-D4Y-T Charge1, Energy1 and Time1 contain accumulated quan- Figure 5. -
Page 21: Overcurrent Comparators
Int. XXXX X111 programmed individually by means of the OCCxDACx bits between 0 and 310mV. OVERCURRENT COMPARATORS Table 6. OCC Thresholds The LTC2949 features two fast differential over-current Threshold OCCxDAC2 OCCxDAC1 OCCxDAC0 [mV] comparators with rail to rail input common mode and programmable threshold followed by configurable filters to suppress input glitches. -
Page 22: Serial Interfaces
PHYSICAL LAYER of the IOVCC pin. Regardless of which configuration is selected, the LTC2949 acts as an SPI slave. The LTC2949 Connecting pin IOVCC to a supply voltage ≥1.8V configures can be operated in addressable mode (SPI & isoSPI) or the serial port for 4-wire SPI. -
Page 23: 2-Wire Isolated Interface (Isospi) Physical Layer
2-wire interface which allows fully isolated operation of nections with limited voltage transients at the isolation the LTC2949. The 2-wire interface provides means to com- barrier. Additional clamping Schottky diodes might be municate to LTC2949 using simple twisted pair cabling. - Page 24 IDLE state if there is no activity on IP/IM for a time In this example, the pulse drive current IDRV will be 10mA, of t . The LTC2949 will be ready to communicate when and the receiver comparators will detect pulses with IP-IM IDLE the core is not in SLEEP and the isoSPI state changes amplitudes greater than ±302mV.
- Page 25 (No Return Pulse if Not in READ Short –1 1. Set SDI = 0 LTC2949 will have IOVCC tied to its local GND. It receives Mode or if Reading a 1-bit) 2. Pulse SCK transmitted pulses and reconstructs the SPI signals in- ternally, as shown in Table 9.
- Page 26 LTC2949 in Addressable/Multidrop Bus Configuration LTC2949 Connected to Reversible isoSPI Ring An LTC2949 can be directly connected to the master in SPI LTC2949 can be connected to one end of a reversible or through an LTC6820 in isoSPI mode. When operating isoSPI ring.
- Page 27 LTC2949 SERIAL INTERFACES Rev A For more information www.analog.com...
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Page 28: Data Link Layer
When LTC2949 is the last element in an isoSPI daisy connects via port B to the 1st element of the daisy chain chain, the DCMD can be used to write to LTC2949 but not using isoSPI, and so on. When the LTC68xx Cell Monitor to read data from the device, because the DCMD is not –... - Page 29 ADCs and cells. The LTC681x devices have several ADC modes with different filter bandwidth and accuracy. Typically, in the 7kHz normal mode, all cells are converted within a time window very close to LTC2949’s fast conver- sion time which is nominal 782µs. For example, the LTC6810 converts all cells within 815µs in the normal mode.
- Page 30 0x0F in the previous RDCV. The following diagram shows details on LTC2949’s fast continuous conversion timing. Fast continuous operation is started by a direct write command that sets bit FACONV and at least one of the channel bits (CH1, CH2, AUX) in register FACTRL.
- Page 31 LTC2949 SERIAL INTERFACES and disable FACONV periodically or to perform repetitive Fast AUX Measurements FSSHT measurements it is recommended to configure It is not possible to change the AUX MUX configuration CH1 for slow and CH2 for fast mode, which ensures the during fast continuous mode (FCM) measurements.
- Page 32 Note 4: CONT0 and MUX0 can be merged to a single 3-write command to FAMUXN, FAMUXP , FACTRL (MOSI: 0xFEF3C7984600010E9516) Note 5: When LTC2949 is in STANDBY state it can be moved to MEASURE state at any time by writing CONT=1. From the write command...
- Page 33 PEC. In case of a PEC mismatch the data will be discarded and an external communication PEC error (EXTCOMMERR) will be flagged in the FAULTS register. DATA Data bytes to be send to or read from LTC2949’s register map. The starting address is given by RADDR and is auto- incremented for every data byte. Rev A For more information www.analog.com...
- Page 34 ADOW, ADOL, ADAX, ADAXD, ADCVAX and ADCVSC (all referred as ADCV commands in this document) are sup- In the configuration where LTC2949 is on top of a daisy ported as broadcast and addressed commands. Addressed chain, after a broadcast RDCV command, the stacked commands are used to address LTC2949 exclusively.
- Page 35 The master shall wait at least 1.26ms between the time fast continuous mode is enabled and the LTC2949’s fast conversion time is typically 0.8ms. Addi- first time any FIFO register is read, to allow the first sample tional processing time is necessary for the results being to be read from the FIFO.
- Page 36 1 0 x x 1 1 x 1 1 1 1 ADCVSC 1 0 x x 1 1 x 0 1 1 1 Table 18. RDCV Style Commands. Used to Read Fast Conversion Results or for Indirect Memory Map Reads from LTC2949 NAME CMD0[7:3]...
- Page 37 DCMD is the recommended way of reading data from the LTC2949 in addressable mode. When LTC2949 is the last ele- ment in a daisy chain, an RDCV has to be used to read data from the LTC2949, as DCMD is not supported by LTC68xx Cell Monitors and therefore does not configure them as shift registers, In default, the LTC2949 will respond to RDCV with the fast mode conversion results as described above (RDCVCONF = 1).
- Page 38 The command or data is bit register group) regarded as valid only if the PEC matches. LTC2949 also attaches the calculated PEC at the end of the data 2. For each bit DIN coming into the PEC register group, it shifts out.
- Page 39 The PEC allows the user to have confidence that the serial once when the microcontroller starts and will initialize a data read from the LTC2949 is valid and has not been cor- PEC15 table array called pec15Table[]. This table will be rupted by any external noise source.
- Page 40 LTC2949 SERIAL INTERFACES /************************************ Copyright 2012 Linear Technology Corp. (LTC) Permission to freely use, copy, modify, and distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies: THIS SOFTWARE IS PROVIDED “AS IS”...
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Page 41: Register Map
LTC2949 REGISTER MAP Rev A For more information www.analog.com... -
Page 42: Register Description
Note: Write 1 to SO bits to request the associated action. Successful write can be checked by a read command directly following the write command. After the action was performed the SO bit will be cleared automatically by LTC2949. Do not write to registers with SO bits, before all SO bits were read as 0. The... - Page 43 Note 9: ADJUPD shall be issued when in STANDBY mode only. The recommended implementation is to set ADJUPD as the last action of the initialization routine, before entering continuous mode. Once ADJUPD is set it takes a maximum of 100ms until LTC2949 has finished the internal update process and the bit ADJUPD is cleared automatically.
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Page 44: Register Map
Still, once it is necessary to clear those registers, memory locking is mandatory to avoid missing any alert and faults reporting. If an alert condition occurs while the memory is locked, LTC2949 will set the corresponding bit after the memory is unlocked by the host. This rule must be followed independent of the core state, as certain faults may also be raised in STANDBY mode. - Page 45 LTC2949 REGISTER DESCRIPTION WAKE-UP WITH DIRECT WAKE-UP PROCEDURE READ COMMANDS \00/ SEND DUMMY BYTE TO WAKE-UP isoSPI \00/ SEND DUMMY BYTE TO WAKE-UP CORE \FEFF9E0840806426/ WRITE REGSCTRL WITH PAGE = 0 AND RDCVCONF/BCREN ACCORDING TO DIRECT/INDIRECT READ MODE \FEF0D1FC80002000/ \FEF0D1FC8001AB32/...
- Page 46 In applications where LTC2949 is connected on top of a daisychain, the bit BCREN in REGSCTRL must be set before being able to read from LTC2949. This is only possible after the boot sequence has finished. Polling of the SLEEP bit being cleared can still be implemented by interleaving the read of OPCTRL with a write to REGSCTRL with BCREN=1 (all other bits 0).
- Page 47 LSBC1. In this case, a C1 register value of 0x 75 5A 10 or 7690768 and the resulting Charge1 is 0.003 VS. For a sense resistor of 300µΩ this corresponds to 10As. LSB values may be calculated easily using the Quick Eval software for the LTC2949 or by using the C/C header files provided in the code section of the LTC2949 (see LTC2949 evaluation board DC2732A manual for details).
- Page 48 LTC2949 REGISTER DESCRIPTION Table 28. Non-Accumulated Results Register Parameters (continued) ADDRESS NAME TYPE DEFAULT PARAMETER UNIT SI/UI Power 2 (Power, P2ASV =0) 5.8368 μ[V 0x99 P2[23:0] 0x00 Power 2 (Voltage, P2ASV=1) 46.875 µV 0x9C I1AVG[23:0] 0x00 Current 1 Moving Average 237.5...
- Page 49 Write overrun, FIFO was filled completely and at least one sample was already overwritten It is recommended to connect LTC2949 always in parallel to a daisy chain. Also, in the scenario where LTC2949 is con- nected at one end of a reversible isoSPI chain, the default communication should be done with direct read commands.
- Page 50 Any other value indicates a failure. Any bits in the STATUS, alerts (0x81-0x87), FAULTS and EXTFAULTS registers are only set to 1 by LTC2949 in case of an event, but never cleared automatically. After the master reads some bits being set, actions should be taken (e.g.
- Page 51 1. After exit from shutdown, bits UVLOA and UVLOD are set. UPDATE is set to 1 when the LTC2949 has finished a measurement cycle and updated the result registers, the accumulation registers, and the tracking registers.
- Page 52 The accumulated quantities are continuously checked against guard values to warn that a register is nearing overflow, nominally set to 90% of each register’s maximum value. When any quantity crosses its guard threshold, the LTC2949 sets the corresponding overflow bit in the status register, generates an alert (if enabled) and continues accumulation.
- Page 53 LTC2949 REGISTER DESCRIPTION Table 35. Voltage, Temperature Threshold Alerts STATVT (0x81) SYMBOL TYPE DEFAULT OPERATION BATH 1: Voltage (VBATP – VBATM) high threshold exceeded BATL 1: Voltage (VBATP – VBATM) low threshold exceeded TEMPH 1: Temperature high threshold exceeded TEMPL...
- Page 54 LTC2949 REGISTER DESCRIPTION Table 40. Time Base Alerts STATTB (0x86) SYMBOL TYPE DEFAULT OPERATION T1TH 1: Time1 threshold exceeded T2TH 1: Time2 threshold exceeded T3TH 1: Time3 threshold exceeded T4TH 1: Time4 threshold exceeded T1OVF 1: Time1 overflow T2OVF 1: Time2 overflow...
- Page 55 LTC2949 REGISTER DESCRIPTION When bits from STATIPM are set to 0, bits from register STATIP(0x82) will stop heartbeat. When a bit of STATIPM register is set to 1, heartbeat is unaffected by the corresponding bits of register STATIP(0x82). Table 44. Current, Power Threshold Alert Mask STATIPM (0x8A)
- Page 56 LTC2949 REGISTER DESCRIPTION When bits from STATTBM are set to 0, bits from register STATTB (0x86) will stop heartbeat. When a bit of STATTBM register is set to 1, heartbeat is unaffected by the corresponding bits of register STATTB (0x86).
- Page 57 LTC2949 REGISTER DESCRIPTION The Accumulator Control and Deadband Registers allow to control the accumulation of Charge1, Energy1, Charge2, Energy2, Charge3 and Energy4 (C1, E1, C2, E2, C3, E4). Accumulation can be enabled, disabled or conditionally enabled based on the sign and absolute value of a measured current. C1 contains accumulated I1, C2 contains accumulated I2, E1 contains accumulated P1 and E2 contains accumulated P2.
- Page 58 LTC2949 REGISTER DESCRIPTION The Time Base Control Register selects between the internal and an external reference clock, and sets the time base parameters when an external reference clock is used. Set PRE[2:0] = 111b or 7d (default) to enable the internal refer- ence clock.
- Page 59 LTC2949 REGISTER DESCRIPTION In slow, high precision mode the auxiliary channel (CHAUX) converts in Round Robin mode two differential inputs signals. For each of the two slots, the inputs multiplexed to MUXP and MUXN can be chosen by programming the corresponding 5-bit setting in the following four registers.
- Page 60 LTC2949 REGISTER DESCRIPTION The GPIO control registers allow to configure the GPIO pins to be either tristate, low, high or toggling at 400kHz by setting the corresponding GPIO CTRL bits in 0xF1 and 0xF2. GPIO4 and GPIO5 can be used as heartbeat pins toggling with a frequency of 400kHz and become static low upon an alert.
- Page 61 LTC2949 REGISTER DESCRIPTION Table 63. GPIO Control FGPIOCTRL (0xF2) SYMBOL TYPE DEFAULT OPERATION [1:0] GPIO1CTRL [1:0] GPIO1-4 CTRL: [00]=Tristate [3:2] GPIO2CTRL [1:0] [01]=LOW(DGND), [5:4] GPIO3CTRL [1:0] [10]=Toggle at 400kHz [11] =HIGH(DVCC) [7:6] GPIO4CTRL [1:0] If set to tristate, the GPIO pins can be used as analog inputs (V8-V12) to the auxiliary channel by choosing the corresponding multiplexer settings according to Table 57.
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Page 62: Register Map
OPERATION RSTUNLCK Writing 0x55 to this register will unlock the RESET function within OPCTRL. After putting LTC2949 into SLEEP mode a writing command to OPCTR with the value 0x80 will issue the reset. Detailed steps to reset LTC2949 are: 1. Write 0 to OPCTRL (0xF0) 2. - Page 63 Mantissa LSB 2^(62-63) (1+0.899994) = 0.5 • 1.899994 = 0.94999 The GUI controlling the LTC2949 demo board supports converting numbers to FLOAT24. The code section of the LTC2949 (https://www.analog.com/en/products/ltc2949.html#product-tools) also provides conversion functions written in C/C for this purpose. LTC2949.cpp contains following conversion functions:...
- Page 64 REGISTER DESCRIPTION Configuration Registers The following registers allow to configure LTC2949 application specific. Please note that LTC2949 must be in STANDBY and an update of these registers must be requested by setting the ADJUPD bit in the Operation Control Register (OPC- TRL) to make changes effective.
- Page 65 REGISTER DESCRIPTION NTC Configuration Registers When bits NTC1 and NTC2 in the ADC Configuration Register are set, LTC2949 reports the result of the corresponding CHAUX slot in temperature by comparing NTC resistance to reference resistors and solving Steinhart-Hart equations. The NTC Configuration Registers allow to set values of Steinhart-Hart coefficients (A,B,C) and reference resistors.
- Page 66 In many applications the LTC2949 measures high voltages using external resistor dividers which suffer from gain errors due to resistor tolerances. The LTC2949 allows to store gain correction factors for the measurement of battery voltage and four programmable MUX settings. E.g.: The LTC2949 will apply gain correction of 0.9 to differential mea- surements between V1 and V2 if registers MUX1GC[23:0] = 0x3ECCCC, MUXPSET1[7:0] = 0x01 and MUXNSET1[7:0] = 0x02, see also Table 57.
- Page 67 REGISTER DESCRIPTION External EEPROM Control Register To prevent data loss when the LTC2949 is not powered, it can store its entire register content in an external EEPROM via its dedicated I C interface. The communication to an EEPROM is controlled by the EEPROM Control Register (EEPROMCTRL).
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Page 68: Application Information
When bits NTC1 or NTC2 in the ADC Configuration Register impact the temperature measurement accuracy. are set, LTC2949 reports the result of the corresponding CHAUX slot in slow high precision mode in temperature by comparing the resistance of a thermistor (NTC) R to a reference resistor and solving the Steinhart-Hart equation. -
Page 69: Sense Resistor Temperature Compensation
The following linear equation system has to be solved to calculate A,B,C using three values, R1(T1), R2(T2), R3(T3) The LTC2949 can be configured to compensate the tem- from a R versus T (in K) resistor table: perature dependency of the used current sense resistors up to 2nd order based on temperature measurements with ⎛... - Page 70 Setup pair these settings will allow for communication up to 50m. For applications that require cables longer than The LTC2949 allows the isoSPI link in each application 50m it is recommended to increase the I to 1mA. This to be optimized for power consumption or for noise compensates for the increased insertion loss in the cable immunity.
- Page 71 LTC2949 APPLICATION INFORMATION For cables under 50m: inductances above 60µH and a 1:1 turns ratio. It is also necessary to use a transformer with less than 2.5µH of = 0.5mA leakage inductance. In terms of pulse shape the primary = (20 • I ) •...
- Page 72 IP and IM lines of the LTC2949. application. The working voltage rating of a transformer The common mode choke will both increase EMI immunity is a key spec when selecting a part for an application.
- Page 73 LTC2949 APPLICATION INFORMATION Table 78. Recommended Transformers AEC- SUPPLIER PART NUMBER TEMP RANGE /60S (W/ LEADS) PINS Q200 WORKING HIPOT Recommended Dual Transformers Pulse HX1188FNL –40°C to 85°C 60V (est) 1.5kV 6.0mm 12.7mm 9.7mm 16SMT – Pulse HX0068ANL –40°C to 85°C 60V (est) 1.5kV...
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Page 74: Current And Voltage Input Filtering
High-Ohmic Resistive Dividers Unused Input Pins V1-V12 Any high voltage to be measured by LTC2949 must be divided down and optionally biased via VREF to move it Input pins V1-V12 can be left floating or connected to GND into the LTC2949’s supply voltage rails ±100mV and into... -
Page 75: Powering The Ltc2949
POWERING THE LTC2949 As any resistive divider is affected by static tolerances, it The LTC2949 requires a single supply voltage of 4.5 to can be calibrated by applying a known input signal and 14V. The maximum supply current is 20mA when active calculating greal from the ADC measurement. - Page 76 LT8304/-1 3V to 100V 2A/150V SO-8E the LTC2949 directly out of a high voltage battery of up to 560V as shown in Figure 29. Minimum load requirement of the flyback converters must be considered which is typically much higher than Isolated supply the sleep current of the LTC2949.
- Page 77 LTC2949 APPLICATION INFORMATION 1mA TO 200mA (V = 3.3V) 47µF 2.7V TO 16V • 1mA TO 300mA (V = 5V) 10µF UVLO • • 1mA TO 450mA (V = 12V) 10µH 10µH 0.8A SYNC 10µF • 47µF OVLO/DC EN/UVLO –...
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Page 78: Package Description
LTC2949 PACKAGE DESCRIPTION LXE Package 48-Lead Plastic Exposed Pad LQFP (7mm × 7mm) (Reference LTC DWG #05-08-1927 Rev B) Exposed Pad Variation AA 9.00 BSC 7.00 BSC 4.15 ±0.20 SEE NOTE: 3 9.00 BSC 7.00 BSC 4.15 ±0.20 C0.30 – 0.50 BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA) -
Page 79: Revision History
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications For more information www.analog.com subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. -
Page 80: Typical Application
Cells Simultaneously. The isoSPI Bus Can Operate Up to 1MHz and Can Be Operated Bidirectionally for Fault Conditions, Such as a Broken Wire or Connector. Includes Internal Passive Cell Balancing Capability of Up to 200mA. Rev A 11/20 www.analog.com ANALOG DEVICES, INC. 2019-2020 For more information www.analog.com...
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