Synchronization Requirement - Analog Devices VisualDSP++ 5.0 Service Manual

Dual-Core Considerations
ADI_PWR_COMMAND_PAIR power_init_table[] = {
{
ADI_PWR_CMD_SET_PROC_VARIANT,(void*)ADI_PWR_PROC_BF561SKBCZ500X
},
{ ADI_PWR_CMD_SET_PACKAGE,(void*)ADI_PWR_PACKAGE_MBGA },
{ ADI_PWR_CMD_SET_VDDEXT, (void*)ADI_PWR_VDDEXT_330 },
{ ADI_PWR_CMD_SET_CLKIN,
{ ADI_PWR_CMD_SET_AUTO_SYNC_ENABLED,
{ ADI_PWR_CMD_END,
};
adi_pwr_Init(power_init_table);

Synchronization Requirement

Blackfin dual-core processors are capable of running one core while the
other core is idle. Power management and EBIU management require that
both cores be placed in the IDLE state when making power management
and EBIU controller changes. If the EBIU module has been initialized,
and the system clock frequency is changed, the SDRAM timing parame-
ters are automatically adjusted. To avoid corruption of SDRAM, the
automatic core synchronization mechanism forces both cores to execute
outside of the SDRAM memory space, while the SDRAM timing parame-
ters are updated.
There are two possible operating modes: running on one core, and
running applications on both cores.
3-6
/* 500 MHz ADSP-BF561 variant */
/* in MBGA packaging */
/* 3.3 V External supplied
to voltage regulator */
(void*) 30 },
/* 30 MHz clock in */
/* enable auto-synchronization */
0 }
/* no more commands after this */
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
NULL },