Setting Control Values in the EBIU Module
For example, SDRAM self-refresh is enabled when the processor mode is
put into "deep sleep" via the power management module.
mation, see "Power Management Module" on page 3-1.
ADI_EBIU_SDRAM_SRFS_DISABLE
ADI_EBIU_SDRAM_SRFS_ENABLE
The default value is specified by the following macro:
#define ADI_EBIU_SDRAM_SRFS_DEFAULT
ADI_EBIU_SDRAM_SRFS_DISABLE
ADI_EBIU_SDRAM_EBUFE
This enumeration specifies whether the EBIU uses external buffers when
several SDRAM devices are used in parallel. This enumeration corre-
sponds to the
EBUFE
ADI_EBIU_SDRAM_EBUFE_DISABLE
ADI_EBIU_SDRAM_EBUFE_ENABLE
The default value is specified by the following macro:
#define ADI_EBIU_SDRAM_EBUFE_DEFAULT
ADI_EBIU_SDRAM_EBUFE_DISABLE
ADI_EBIU_SDRAM_PUPSD
This enumeration specifies whether the power-up start sequence is delayed
by 15
cycles. This enumeration corresponds to the
SCLK
register.
EBIU_SDGCTL
ADI_EBIU_SDRAM_PUPSD_NODELAY
ADI_EBIU_SDRAM_PUPSD_15CYCLES
4-42
Disables SDRAM self-refresh on inactivity.
Enables SDRAM self-refresh on inactivity.
bit in the
EBIU_SDGCTL
Disables the use of external buffers when several
SDRAM devices are used in parallel.
Enables the use of external buffers when several
SDRAM devices are used in parallel.
No delay to the power-up start sequence.
Power-up start sequence is delayed by 15
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
For more infor-
register.
PUPSD
bit in the
cycles.
SCLK
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