Running Applications On Both Cores - Analog Devices VisualDSP++ 5.0 Service Manual

Dual-Core Considerations
The other method is to disable the PLL wakeup bit in the
ister and go to IDLE. If this is done in the assembler, the following code
can take the place of the startup code:
#include <defBF561.h>
.section program;
start:
P0.H = HI(SICB_IWR0); P0.L = LO(SICB_IWR0);
R0 = 0;
[P0] = R0;
IDLE;
.start.end:
.global start;
.type start,STT_FUNC;

Running Applications on Both Cores

In this case, both cores execute code. Both cores need to synchronize to
ensure that both cores are IDLE and, in some cases, do not execute out of
SDRAM as described in the requirement above. There are two choices:
1) define your own synchronization strategy, or 2) use the built-in syn-
chronization provided by the power management module (which must be
enabled by a separate command).
To use the built-in synchronization, include the following command value
pair to
adi_pwr_Init()
{ ADI_PWR_CMD_SET_AUTO_SYNC_ENABLED, NULL }
Once activated, the built-in synchronization has exclusive control over
supplemental interrupt 0 and chains an appropriate interrupt handler to
the appropriate IVG level using the interrupt manager. This prevents the
3-8
on both cores:
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
reg-
SICB_IWR0