Adi_Pwr_Ssel - Analog Devices VisualDSP++ 5.0 Service Manual

Public Data Types and Enumerations
Table 3-7. PM Module Return Values (Cont'd)
Return Value
ADI_PWR_RESULT_INVALID_VR_FREQ
ADI_PWR_RESULT_INVALID_VR_GAIN
ADI_PWR_RESULT_INVALID_VR_WAKE
ADI_PWR_RESULT_INVALID_VR_PHYWE
ADI_PWR_RESULT_INVALID_VR_CANWE
ADI_PWR_RESULT_INVALID_VR_USBWE
ADI_PWR_RESULT_INVALID_VR_CLKBUFOE
ADI_PWR_RESULT_INVALID_VR_CKELOW
ADI_PWR_RESULT_INVALID_VR_USBWE

ADI_PWR_SSEL

This data type defines the system clock divider bit field in the
register. Valid values are:
ADI_PWR_SSEL_1
ADI_PWR_SSEL_2
ADI_PWR_SSEL_3
ADI_PWR_SSEL_4
ADI_PWR_SSEL_5
ADI_PWR_SSEL_6
ADI_PWR_SSEL_7
ADI_PWR_SSEL_8
ADI_PWR_SSEL_9
ADI_PWR_SSEL_10
ADI_PWR_SSEL_11
ADI_PWR_SSEL_12
3-52
Explanation
FREQ
GAIN
WAKE
PHYWE
CAN
USB
CLKBUFOE
CKELOW
USBWE
Divides voltage core oscillator frequency by 1.
Divides voltage core oscillator frequency by 2.
Divides voltage core oscillator frequency by 3.
Divides voltage core oscillator frequency by 4.
Divides voltage core oscillator frequency by 5.
Divides voltage core oscillator frequency by 6.
Divides voltage core oscillator frequency by 7.
Divides voltage core oscillator frequency by 8.
Divides voltage core oscillator frequency by 9.
Divides voltage core oscillator frequency by 10.
Divides voltage core oscillator frequency by 11.
Divides voltage core oscillator frequency by 12.
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
value is invalid.
value is invalid.
value is invalid.
value is invalid.
wakeup value is invalid.
wakeup value is invalid.
value is invalid.
value is invalid.
wakeup value is invalid.
PLL_DIV