Adi_Ebiu_Asynch_Setup_Time; Adi_Ebiu_Asynch_Transition_Time - Analog Devices VisualDSP++ 5.0 Service Manual

ADI_EBIU_ASYNCH_HT_0_CYCLES
ADI_EBIU_ASYNCH_HT_1_CYCLES
ADI_EBIU_ASYNCH_HT_2_CYCLES
ADI_EBIU_ASYNCH_HT_3_CYCLES

ADI_EBIU_ASYNCH_SETUP_TIME

The setup time for the asynchronous memory controller is specified in the
field of an
bank_time
ture. That field is of type "ADI_EBIU_TIMING_VALUE", which in this
case can either specify a number of cycles or an
value, but not both. When cycles are used, the
ADI_EBIU_ASYNCH_SETUP_TIME
of setup time. It corresponds to the
in the asynchronous memory bank control 0 register (for banks 0 and 1)
or the asynchronous memory bank control 1 register (for banks 2 and 3).
ADI_EBIU_ASYNCH_ST_4_CYCLES
ADI_EBIU_ASYNCH_ST_1_CYCLES
ADI_EBIU_ASYNCH_ST_2_CYCLES
ADI_EBIU_ASYNCH_ST_3_CYCLES

ADI_EBIU_ASYNCH_TRANSITION_TIME

The transition time for the asynchronous memory controller is specified
in the
bank_time
structure. That field is of type "ADI_EBIU_TIMING_VALUE", which
in this case can either specify a number of cycles or an
"ADI_EBIU_TIME"
ADI_EBIU_ASYNCH_TRANSITION_TIME
cycles of transition time. It corresponds to the
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
External Bus Interface Unit Module
"ADI_EBIU_ASYNCH_BANK_TIMING"
enumeration specifies the number of cycles
field of an "ADI_EBIU_ASYNCH_BANK_TIMING"
value, but not both. When cycles are used, the
0 cycles hold time
1 cycles hold time
2 cycles hold time
3 cycles hold time
"ADI_EBIU_TIME"
bit (where is the bank number)
BXST X
4 cycles setup time
1 cycles setup time
2 cycles setup time
3 cycles setup time
enumeration specifies the number of
bit (where
BXHT
struc-
is the
X
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