Analog Devices VisualDSP++ 5.0 Service Manual page 71

SIC allows peripheral interrupts to be mapped to any of the CEC's
general-purpose IVG levels and controls whether these interrupts wake the
processor from an idled operating mode.
In systems that employ Blackfin processors, often there are more potential
interrupt sources than IVG levels. As stated above, some events (such as
NMI) map one-to-one to an IVG level. Other events, typically infrequent
interrupts such as peripheral error interrupts, are often "ganged" in a sin-
gle IVG level.
The interrupt manager allows the application to execute complete control
over how interrupts are handled, whether they are masked or unmasked,
whether they mapped one-to-one or ganged together, whether the proces-
sor should be awakened to service an interrupt, and so on. The interrupt
manager also allows the creation of interrupt handler chains. An interrupt
handler is a C-callable function that is provided by the application to pro-
cess an interrupt. Through the interrupt manager, the application can
hook in any number of interrupt handlers for any IVG level. When
multiple events are ganged to a single IVG level, this allows each handler
to be designed independently from any other and allows the application to
process these interrupts in a straightforward manner.
Further, the interrupt manager processes only those IVG levels and system
interrupts that the application directs the interrupt manager to control.
This allows the application developer to have complete unfettered access
to any IVG level or system interrupt to manually control interrupts.
Multi-core Blackfin processors extend this capability by including one sys-
tem interrupt controller and one core event controller for each core. This
provides maximum flexibility by allowing application developers to decide
how to map interrupts to individual cores, multiple cores, and so on.
When using multi-core Blackfin processors, typically one interrupt man-
ager for each core is used. Because there is no reason to provide multiple
interrupt managers on single-core devices, this service is not supported.
Application developers should not attempt to instantiate more than one
interrupt manager per core.
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
Interrupt Manager
2-3