Analog Devices VisualDSP++ 5.0 Service Manual page 130

Power Management API Reference
Table 3-3. adi_pwr_Init Command-Value Pairs (Cont'd)
Command
ADI_PWR_CMD_SET_INPUT_DELAY
ADI_PWR_CMD_SET_OUTPUT_DELAY
The
adi_pwr_Init
are ignored with the
adi_pwr_Init
result code returned.
Table 3-4 lists valid command-value pairs for an ADSP-BF561 dual-core
processor.
Table 3-4. ADSP-BF561 Dual-Core Processor
Command-Value Pairs
Command
Commands relevant to ADSP-BF561 dual-core processor only.
ADI_PWR_CMD_SET_AUTO_SYNC_ENABLED
ADI_PWR_CMD_SET_COREB_SUPP_INT0_IVG
3-26
Description
ADI_PWR_INPUT_DELAY
approximately 200 ps of delay to the time when inputs
are latched on the external memory interface. See
"ADI_PWR_INPUT_DELAY" on page
ADI_PWR_OUTPUT_DELAY
approximately 200 ps of delay to external memory out-
put signals. See
page 3-48.
function can only be called once. Subsequent calls to
ADI_PWR_RESULT_ALREADY_INITIALIZED
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
value specifies whether to add
value specifies whether to add
"ADI_PWR_OUTPUT_DELAY" on
Description
Instructs the power management
module to use its built-in mech-
anism for synchronizing the
cores across changes to the PLL.
Use NULL as the associated
value. This command is to be
passed to
adi_pwr_Init()
both cores.
IVG level that is assigned to sup-
plemental interrupt 0 on core B.
This command is passed to
adi_pwr_Init()
only.
3-48.
on
on core B