Adi_Pwr_Setfreq - Analog Devices VisualDSP++ 5.0 Service Manual

adi_pwr_SetFreq

Description
This function sets the PLL controller to provide
close as possible to the requested values (in Hz). If the voltage regulator is
not disabled, it is adjusted (where necessary) to provide the minimum
voltage that can sustain the requested frequencies.
The processor is idled to affect the changes.
This function always finds a solution where the
PLL_DIV
difference between the requested and obtained values is minimized.
To determine the values set by this function, use
Prototype
ADI_PWR_RESULT adi_pwr_SetFreq(
const u32 fcclk,
const u32 fsclk,
const ADI_PWR_DF df);
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
register is unity. If the PLL input divider is requested, the
Power Management Module
and
CCLK
CSEL
adi_pwr_GetFreq
values as
SCLK
divider in the
.
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